Home
last modified time | relevance | path

Searched refs:CLK_TOP_APLL2_DIV0 (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h145 #define CLK_TOP_APLL2_DIV0 127 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h145 #define CLK_TOP_APLL2_DIV0 127 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h145 #define CLK_TOP_APLL2_DIV0 127 macro
/linux-4.4.14/include/dt-bindings/clock/
Dmt8173-clk.h145 #define CLK_TOP_APLL2_DIV0 127 macro
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h145 #define CLK_TOP_APLL2_DIV0 127 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h145 #define CLK_TOP_APLL2_DIV0 127 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h145 #define CLK_TOP_APLL2_DIV0 127 macro
/linux-4.4.14/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi447 <&topckgen CLK_TOP_APLL2_DIV0>,
/linux-4.4.14/drivers/clk/mediatek/
Dclk-mt8173.c587 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),