Searched refs:CLK_TOP_DDRPHYCFG_SEL (Results 1 – 16 of 16) sorted by relevance
| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| D | mt8173-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| D | mt8173-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| /linux-4.4.14/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| D | mt8173-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| D | mt8173-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| D | mt8173-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| D | mt8173-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| D | mt8173-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| /linux-4.4.14/drivers/clk/mediatek/ |
| D | clk-mt8173.c | 533 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
904 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_clk_enable_critical()
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| D | clk-mt8135.c | 389 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
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