Searched refs:CLK_TOP_SYSPLL3_D2 (Results 1 – 10 of 10) sorted by relevance
20 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.51 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
70 #define CLK_TOP_SYSPLL3_D2 52 macro
383 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
103 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),