Searched refs:CLK_TOP_SYSPLL4_D2 (Results 1 – 9 of 9) sorted by relevance
22 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
73 #define CLK_TOP_SYSPLL4_D2 55 macro
106 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),