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Searched refs:CLK_TZPC4 (Results 1 – 32 of 32) sorted by relevance

/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dexynos5250.h134 #define CLK_TZPC4 328 macro
Dexynos5420.h100 #define CLK_TZPC4 307 macro
Dexynos3250.h154 #define CLK_TZPC4 150 macro
Dexynos4415.h210 #define CLK_TZPC4 215 macro
/linux-4.4.14/include/dt-bindings/clock/
Dexynos5250.h134 #define CLK_TZPC4 328 macro
Dexynos5420.h100 #define CLK_TZPC4 307 macro
Dexynos3250.h154 #define CLK_TZPC4 150 macro
Dexynos4415.h210 #define CLK_TZPC4 215 macro
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dexynos5250.h134 #define CLK_TZPC4 328 macro
Dexynos5420.h100 #define CLK_TZPC4 307 macro
Dexynos3250.h154 #define CLK_TZPC4 150 macro
Dexynos4415.h210 #define CLK_TZPC4 215 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dexynos5250.h134 #define CLK_TZPC4 328 macro
Dexynos5420.h100 #define CLK_TZPC4 307 macro
Dexynos3250.h154 #define CLK_TZPC4 150 macro
Dexynos4415.h210 #define CLK_TZPC4 215 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dexynos5250.h134 #define CLK_TZPC4 328 macro
Dexynos5420.h100 #define CLK_TZPC4 307 macro
Dexynos3250.h154 #define CLK_TZPC4 150 macro
Dexynos4415.h210 #define CLK_TZPC4 215 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dexynos5250.h134 #define CLK_TZPC4 328 macro
Dexynos5420.h100 #define CLK_TZPC4 307 macro
Dexynos3250.h154 #define CLK_TZPC4 150 macro
Dexynos4415.h210 #define CLK_TZPC4 215 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dexynos5250.h134 #define CLK_TZPC4 328 macro
Dexynos5420.h100 #define CLK_TZPC4 307 macro
Dexynos3250.h154 #define CLK_TZPC4 150 macro
Dexynos4415.h210 #define CLK_TZPC4 215 macro
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos5250.c663 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
Dclk-exynos4415.c649 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
Dclk-exynos3250.c478 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
Dclk-exynos5420.c1092 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),