Home
last modified time | relevance | path

Searched refs:CLK_TZPC6 (Results 1 – 32 of 32) sorted by relevance

/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dexynos5250.h136 #define CLK_TZPC6 330 macro
Dexynos5420.h102 #define CLK_TZPC6 309 macro
Dexynos3250.h143 #define CLK_TZPC6 139 macro
Dexynos4415.h198 #define CLK_TZPC6 203 macro
/linux-4.4.14/include/dt-bindings/clock/
Dexynos5250.h136 #define CLK_TZPC6 330 macro
Dexynos5420.h102 #define CLK_TZPC6 309 macro
Dexynos3250.h143 #define CLK_TZPC6 139 macro
Dexynos4415.h198 #define CLK_TZPC6 203 macro
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dexynos5250.h136 #define CLK_TZPC6 330 macro
Dexynos5420.h102 #define CLK_TZPC6 309 macro
Dexynos3250.h143 #define CLK_TZPC6 139 macro
Dexynos4415.h198 #define CLK_TZPC6 203 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dexynos5250.h136 #define CLK_TZPC6 330 macro
Dexynos5420.h102 #define CLK_TZPC6 309 macro
Dexynos3250.h143 #define CLK_TZPC6 139 macro
Dexynos4415.h198 #define CLK_TZPC6 203 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dexynos5250.h136 #define CLK_TZPC6 330 macro
Dexynos5420.h102 #define CLK_TZPC6 309 macro
Dexynos3250.h143 #define CLK_TZPC6 139 macro
Dexynos4415.h198 #define CLK_TZPC6 203 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dexynos5250.h136 #define CLK_TZPC6 330 macro
Dexynos5420.h102 #define CLK_TZPC6 309 macro
Dexynos3250.h143 #define CLK_TZPC6 139 macro
Dexynos4415.h198 #define CLK_TZPC6 203 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dexynos5250.h136 #define CLK_TZPC6 330 macro
Dexynos5420.h102 #define CLK_TZPC6 309 macro
Dexynos3250.h143 #define CLK_TZPC6 139 macro
Dexynos4415.h198 #define CLK_TZPC6 203 macro
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos5250.c665 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
Dclk-exynos4415.c629 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
Dclk-exynos3250.c460 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
Dclk-exynos5420.c1094 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),