| /linux-4.4.14/include/dt-bindings/clock/ |
| D | exynos5410.h | 22 #define CLK_UART0 257 macro
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| D | pistachio-clk.h | 42 #define CLK_UART0 48 macro
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| D | exynos5250.h | 95 #define CLK_UART0 289 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | s5pv210.h | 164 #define CLK_UART0 143 macro
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| D | exynos4.h | 152 #define CLK_UART0 312 macro
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| D | exynos3250.h | 220 #define CLK_UART0 216 macro
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| D | exynos4415.h | 286 #define CLK_UART0 291 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 22 #define CLK_UART0 257 macro
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| D | pistachio-clk.h | 42 #define CLK_UART0 48 macro
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| D | exynos5250.h | 95 #define CLK_UART0 289 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | s5pv210.h | 164 #define CLK_UART0 143 macro
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| D | exynos4.h | 152 #define CLK_UART0 312 macro
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| D | exynos3250.h | 220 #define CLK_UART0 216 macro
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| D | exynos4415.h | 286 #define CLK_UART0 291 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 22 #define CLK_UART0 257 macro
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| D | pistachio-clk.h | 42 #define CLK_UART0 48 macro
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| D | exynos5250.h | 95 #define CLK_UART0 289 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | s5pv210.h | 164 #define CLK_UART0 143 macro
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| D | exynos4.h | 152 #define CLK_UART0 312 macro
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| D | exynos3250.h | 220 #define CLK_UART0 216 macro
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| D | exynos4415.h | 286 #define CLK_UART0 291 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 22 #define CLK_UART0 257 macro
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| D | pistachio-clk.h | 42 #define CLK_UART0 48 macro
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| D | exynos5250.h | 95 #define CLK_UART0 289 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | s5pv210.h | 164 #define CLK_UART0 143 macro
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| D | exynos4.h | 152 #define CLK_UART0 312 macro
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| D | exynos3250.h | 220 #define CLK_UART0 216 macro
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| D | exynos4415.h | 286 #define CLK_UART0 291 macro
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 22 #define CLK_UART0 257 macro
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| D | pistachio-clk.h | 42 #define CLK_UART0 48 macro
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| D | exynos5250.h | 95 #define CLK_UART0 289 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | s5pv210.h | 164 #define CLK_UART0 143 macro
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| D | exynos4.h | 152 #define CLK_UART0 312 macro
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| D | exynos3250.h | 220 #define CLK_UART0 216 macro
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| D | exynos4415.h | 286 #define CLK_UART0 291 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 22 #define CLK_UART0 257 macro
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| D | pistachio-clk.h | 42 #define CLK_UART0 48 macro
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| D | exynos5250.h | 95 #define CLK_UART0 289 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | s5pv210.h | 164 #define CLK_UART0 143 macro
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| D | exynos4.h | 152 #define CLK_UART0 312 macro
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| D | exynos3250.h | 220 #define CLK_UART0 216 macro
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| D | exynos4415.h | 286 #define CLK_UART0 291 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 22 #define CLK_UART0 257 macro
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| D | pistachio-clk.h | 42 #define CLK_UART0 48 macro
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| D | exynos5250.h | 95 #define CLK_UART0 289 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | s5pv210.h | 164 #define CLK_UART0 143 macro
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| D | exynos4.h | 152 #define CLK_UART0 312 macro
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| D | exynos3250.h | 220 #define CLK_UART0 216 macro
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| D | exynos4415.h | 286 #define CLK_UART0 291 macro
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| /linux-4.4.14/drivers/clk/zte/ |
| D | clk-zx296702.c | 49 #define CLK_UART0 (lsp1crpm_base + 0x20) macro
692 ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1); in zx296702_lsp1_clocks_init()
696 zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31); in zx296702_lsp1_clocks_init()
698 zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0); in zx296702_lsp1_clocks_init()
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| /linux-4.4.14/Documentation/devicetree/bindings/clock/ |
| D | exynos5410-clock.txt | 43 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | exynos3250-clock.txt | 55 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 158 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
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| D | clk-exynos5250.c | 618 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
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| D | clk-s5pv210.c | 617 GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
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| D | clk-exynos4415.c | 856 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
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| D | clk-exynos3250.c | 653 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
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| D | clk-exynos5420.c | 1027 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
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| D | clk-exynos4.c | 981 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | exynos5410.dtsi | 198 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | s5pv210.dtsi | 336 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
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| D | exynos3250.dtsi | 436 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
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| D | exynos4415.dtsi | 428 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
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| D | exynos4.dtsi | 432 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | exynos5250.dtsi | 1072 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | exynos5420.dtsi | 1150 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| /linux-4.4.14/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 38 GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
|