| /linux-4.4.14/include/dt-bindings/clock/ |
| D | exynos5410.h | 23 #define CLK_UART1 258 macro
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| D | pistachio-clk.h | 43 #define CLK_UART1 49 macro
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| D | exynos5250.h | 96 #define CLK_UART1 290 macro
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| D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| D | s5pv210.h | 163 #define CLK_UART1 142 macro
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| D | exynos4.h | 153 #define CLK_UART1 313 macro
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| D | exynos3250.h | 219 #define CLK_UART1 215 macro
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| D | exynos4415.h | 285 #define CLK_UART1 290 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 23 #define CLK_UART1 258 macro
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| D | pistachio-clk.h | 43 #define CLK_UART1 49 macro
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| D | exynos5250.h | 96 #define CLK_UART1 290 macro
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| D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| D | s5pv210.h | 163 #define CLK_UART1 142 macro
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| D | exynos4.h | 153 #define CLK_UART1 313 macro
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| D | exynos3250.h | 219 #define CLK_UART1 215 macro
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| D | exynos4415.h | 285 #define CLK_UART1 290 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 23 #define CLK_UART1 258 macro
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| D | pistachio-clk.h | 43 #define CLK_UART1 49 macro
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| D | exynos5250.h | 96 #define CLK_UART1 290 macro
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| D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| D | s5pv210.h | 163 #define CLK_UART1 142 macro
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| D | exynos4.h | 153 #define CLK_UART1 313 macro
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| D | exynos3250.h | 219 #define CLK_UART1 215 macro
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| D | exynos4415.h | 285 #define CLK_UART1 290 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 23 #define CLK_UART1 258 macro
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| D | pistachio-clk.h | 43 #define CLK_UART1 49 macro
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| D | exynos5250.h | 96 #define CLK_UART1 290 macro
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| D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| D | s5pv210.h | 163 #define CLK_UART1 142 macro
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| D | exynos4.h | 153 #define CLK_UART1 313 macro
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| D | exynos3250.h | 219 #define CLK_UART1 215 macro
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| D | exynos4415.h | 285 #define CLK_UART1 290 macro
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 23 #define CLK_UART1 258 macro
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| D | pistachio-clk.h | 43 #define CLK_UART1 49 macro
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| D | exynos5250.h | 96 #define CLK_UART1 290 macro
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| D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| D | s5pv210.h | 163 #define CLK_UART1 142 macro
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| D | exynos4.h | 153 #define CLK_UART1 313 macro
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| D | exynos3250.h | 219 #define CLK_UART1 215 macro
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| D | exynos4415.h | 285 #define CLK_UART1 290 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 23 #define CLK_UART1 258 macro
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| D | pistachio-clk.h | 43 #define CLK_UART1 49 macro
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| D | exynos5250.h | 96 #define CLK_UART1 290 macro
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| D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| D | s5pv210.h | 163 #define CLK_UART1 142 macro
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| D | exynos4.h | 153 #define CLK_UART1 313 macro
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| D | exynos3250.h | 219 #define CLK_UART1 215 macro
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| D | exynos4415.h | 285 #define CLK_UART1 290 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 23 #define CLK_UART1 258 macro
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| D | pistachio-clk.h | 43 #define CLK_UART1 49 macro
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| D | exynos5250.h | 96 #define CLK_UART1 290 macro
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| D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| D | s5pv210.h | 163 #define CLK_UART1 142 macro
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| D | exynos4.h | 153 #define CLK_UART1 313 macro
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| D | exynos3250.h | 219 #define CLK_UART1 215 macro
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| D | exynos4415.h | 285 #define CLK_UART1 290 macro
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| /linux-4.4.14/drivers/clk/zte/ |
| D | clk-zx296702.c | 50 #define CLK_UART1 (lsp1crpm_base + 0x24) macro
703 ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1); in zx296702_lsp1_clocks_init()
705 zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1); in zx296702_lsp1_clocks_init()
707 zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0); in zx296702_lsp1_clocks_init()
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 159 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
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| D | clk-exynos5250.c | 619 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
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| D | clk-s5pv210.c | 616 GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
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| D | clk-exynos4415.c | 855 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
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| D | clk-exynos3250.c | 652 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
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| D | clk-exynos5420.c | 1029 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
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| D | clk-exynos4.c | 983 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | exynos5410.dtsi | 207 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| D | s5pv210.dtsi | 348 clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
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| D | exynos3250.dtsi | 447 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
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| D | exynos4415.dtsi | 437 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
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| D | exynos4.dtsi | 443 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| D | exynos5250.dtsi | 1077 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| D | exynos5420.dtsi | 1155 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| /linux-4.4.14/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 39 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
|