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Searched refs:CLK_UART2 (Results 1 – 57 of 57) sorted by relevance

/linux-4.4.14/include/dt-bindings/clock/
Dexynos5410.h24 #define CLK_UART2 259 macro
Dexynos5250.h97 #define CLK_UART2 291 macro
Dexynos5420.h68 #define CLK_UART2 259 macro
Ds5pv210.h162 #define CLK_UART2 141 macro
Dexynos4.h154 #define CLK_UART2 314 macro
Dexynos4415.h284 #define CLK_UART2 289 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dexynos5410.h24 #define CLK_UART2 259 macro
Dexynos5250.h97 #define CLK_UART2 291 macro
Dexynos5420.h68 #define CLK_UART2 259 macro
Ds5pv210.h162 #define CLK_UART2 141 macro
Dexynos4.h154 #define CLK_UART2 314 macro
Dexynos4415.h284 #define CLK_UART2 289 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dexynos5410.h24 #define CLK_UART2 259 macro
Dexynos5250.h97 #define CLK_UART2 291 macro
Dexynos5420.h68 #define CLK_UART2 259 macro
Ds5pv210.h162 #define CLK_UART2 141 macro
Dexynos4.h154 #define CLK_UART2 314 macro
Dexynos4415.h284 #define CLK_UART2 289 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dexynos5410.h24 #define CLK_UART2 259 macro
Dexynos5250.h97 #define CLK_UART2 291 macro
Dexynos5420.h68 #define CLK_UART2 259 macro
Ds5pv210.h162 #define CLK_UART2 141 macro
Dexynos4.h154 #define CLK_UART2 314 macro
Dexynos4415.h284 #define CLK_UART2 289 macro
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dexynos5410.h24 #define CLK_UART2 259 macro
Dexynos5250.h97 #define CLK_UART2 291 macro
Dexynos5420.h68 #define CLK_UART2 259 macro
Ds5pv210.h162 #define CLK_UART2 141 macro
Dexynos4.h154 #define CLK_UART2 314 macro
Dexynos4415.h284 #define CLK_UART2 289 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dexynos5410.h24 #define CLK_UART2 259 macro
Dexynos5250.h97 #define CLK_UART2 291 macro
Dexynos5420.h68 #define CLK_UART2 259 macro
Ds5pv210.h162 #define CLK_UART2 141 macro
Dexynos4.h154 #define CLK_UART2 314 macro
Dexynos4415.h284 #define CLK_UART2 289 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dexynos5410.h24 #define CLK_UART2 259 macro
Dexynos5250.h97 #define CLK_UART2 291 macro
Dexynos5420.h68 #define CLK_UART2 259 macro
Ds5pv210.h162 #define CLK_UART2 141 macro
Dexynos4.h154 #define CLK_UART2 314 macro
Dexynos4415.h284 #define CLK_UART2 289 macro
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dexynos5250-clock.txt39 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos5420-clock.txt40 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos4-clock.txt41 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos5410.c160 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
Dclk-exynos5250.c620 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
Dclk-s5pv210.c615 GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
Dclk-exynos4415.c854 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
Dclk-exynos5420.c1031 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
Dclk-exynos4.c985 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
/linux-4.4.14/arch/arm/boot/dts/
Dexynos5410.dtsi216 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Ds5pv210.dtsi360 clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
Dexynos4415.dtsi446 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
Dexynos4.dtsi454 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos5250.dtsi1082 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
Dexynos5420.dtsi1160 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;