Searched refs:CPG_DIV6_DIV (Results 1 – 1 of 1) sorted by relevance
22 #define CPG_DIV6_DIV(d) ((d) & 0x3f) macro48 | CPG_DIV6_DIV(clock->div - 1); in cpg_div6_clock_enable()120 clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); in cpg_div6_clock_set_rate()