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Searched refs:EVERGREEN_CRTC2_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Devergreen_reg.h226 #define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) macro
Devergreen.c111 EVERGREEN_CRTC2_REGISTER_OFFSET,
4561 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4572 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4638 …afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4781 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in evergreen_irq_set()
4794 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_irq_set()
4819 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); in evergreen_irq_set()
4843 …ev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4853 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4873 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
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Dradeon_display.c1552 EVERGREEN_CRTC2_REGISTER_OFFSET, in radeon_afmt_init()
1887 EVERGREEN_CRTC2_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1889 EVERGREEN_CRTC2_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dsi.c5955 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5968 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6201 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in si_irq_set()
6216 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in si_irq_set()
6261 …ev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in si_irq_ack()
6284 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6288 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6290 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
Dradeon_dp_mst.c16 EVERGREEN_CRTC2_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c7329 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7342 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7612 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in cik_irq_set()
7627 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set()
7679 EVERGREEN_CRTC2_REGISTER_OFFSET); in cik_irq_ack()
7707 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_ack()
7713 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7715 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c660 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | in radeon_card_posted()
Devergreen_cs.c1030 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1038 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2232 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()