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Searched refs:EVERGREEN_CRTC4_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Devergreen_reg.h228 #define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) macro
Devergreen.c113 EVERGREEN_CRTC4_REGISTER_OFFSET,
4565 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4576 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4640 …afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4785 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in evergreen_irq_set()
4800 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_irq_set()
4821 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); in evergreen_irq_set()
4847 …ev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4855 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4888 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
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Dradeon_display.c1554 EVERGREEN_CRTC4_REGISTER_OFFSET, in radeon_afmt_init()
1901 EVERGREEN_CRTC4_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1903 EVERGREEN_CRTC4_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dsi.c5959 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5972 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6205 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in si_irq_set()
6222 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in si_irq_set()
6265 …ev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); in si_irq_ack()
6299 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6303 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6305 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
Dradeon_dp_mst.c18 EVERGREEN_CRTC4_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c7333 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7346 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7616 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in cik_irq_set()
7633 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set()
7685 EVERGREEN_CRTC4_REGISTER_OFFSET); in cik_irq_ack()
7724 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_ack()
7730 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7732 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c664 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | in radeon_card_posted()
Devergreen_cs.c1032 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1040 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2238 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()