Searched refs:FPGA_IRQ_SET_CLR (Results 1 – 1 of 1) sorted by relevance
26 #define FPGA_IRQ_SET_CLR 0x10 macro44 pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask; in cplds_irq_handler()59 set = readl(fpga->base + FPGA_IRQ_SET_CLR); in cplds_irq_mask_ack()60 writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR); in cplds_irq_mask_ack()137 writel(0, fpga->base + FPGA_IRQ_SET_CLR); in cplds_probe()