Searched refs:IMX6QDL_CLK_IPU1_DI1_SEL (Results 1 – 10 of 10) sorted by relevance
52 #define IMX6QDL_CLK_IPU1_DI1_SEL 40 macro
119 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
252 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
308 …clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1… in imx6q_clocks_init()517 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); in imx6q_clocks_init()