Searched refs:IMX6QDL_CLK_IPU2_DI1_SEL (Results 1 – 9 of 9) sorted by relevance
54 #define IMX6QDL_CLK_IPU2_DI1_SEL 42 macro
253 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
310 …clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2… in imx6q_clocks_init()519 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); in imx6q_clocks_init()