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Searched refs:MI_LOAD_REGISTER_IMM (Results 1 – 10 of 10) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_mocs.c191 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES)); in emit_mocs_control_table()
250 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2)); in emit_mocs_l3cc_table()
Dintel_lrc.c923 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); in intel_execlists_submission()
1097 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); in intel_logical_ring_workarounds_emit()
1161 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); in gen8_emit_flush_coherentl3_wa()
1345 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); in gen9_init_perctx_bb()
1561 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); in intel_logical_ring_emit_pdps()
2268 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); in populate_lr_context()
2270 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); in populate_lr_context()
2323 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); in populate_lr_context()
2355 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); in populate_lr_context()
Di915_cmd_parser.c125 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
1032 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) in check_cmd()
1047 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && in check_cmd()
Di915_gem_context.c556 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); in mi_set_context()
581 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); in mi_set_context()
Di915_gem_execbuffer.c1116 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_reset_gen7_sol_offsets()
1243 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_gem_ringbuffer_submission()
Di915_gem_gtt.c663 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in gen8_write_pdp()
666 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in gen8_write_pdp()
1664 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); in hsw_mm_switch()
1701 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); in gen7_mm_switch()
Dintel_ringbuffer.c736 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); in intel_ring_workarounds_emit()
1327 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); in gen6_signal()
Di915_gem.c4653 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_gem_l3_remap()
Di915_reg.h353 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) macro
Dintel_display.c11126 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in intel_gen7_queue_flip()