Searched refs:MSTP (Results 1 – 8 of 8) sorted by relevance
| /linux-4.4.14/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7343.c | 137 #define MSTP(_parent, _reg, _bit, _flags) \ macro
151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
154 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
156 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
157 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
158 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
159 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
[all …]
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| D | clock-sh7366.c | 140 #define MSTP(_parent, _reg, _bit, _flags) \ macro
154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
162 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
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| /linux-4.4.14/Documentation/devicetree/bindings/clock/ |
| D | renesas,cpg-mstp-clocks.txt | 1 * Renesas CPG Module Stop (MSTP) Clocks
7 Clocks are referenced by user nodes by the MSTP node phandle and the clock
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
19 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
20 - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
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| D | renesas,r8a7778-cpg-clocks.txt | 6 CPG Module Stop (MSTP) Clocks.
17 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
18 through an MSTP clock should refer to the CPG device node in their
39 - CPG/MSTP Clock Domain member device node:
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| D | renesas,r8a7779-cpg-clocks.txt | 6 CPG Module Stop (MSTP) Clocks.
19 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
20 through an MSTP clock should refer to the CPG device node in their
41 - CPG/MSTP Clock Domain member device node:
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| D | renesas,rz-cpg-clocks.txt | 6 CPG Module Stop (MSTP) Clocks.
21 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
22 through an MSTP clock should refer to the CPG device node in their
43 - CPG/MSTP Clock Domain member device node:
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| D | renesas,rcar-gen2-cpg-clocks.txt | 6 CPG Module Stop (MSTP) Clocks.
27 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
28 through an MSTP clock should refer to the CPG device node in their
51 - CPG/MSTP Clock Domain member device node:
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | r7s72100.dtsi | 92 /* MSTP clocks */
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