| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | exynos7-clk.h | 82 #define SCLK_UART0 2 macro
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| D | s5pv210.h | 200 #define SCLK_UART0 175 macro
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| D | rk3188-cru-common.h | 29 #define SCLK_UART0 64 macro
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| D | rk3288-cru.h | 41 #define SCLK_UART0 77 macro
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| D | rk3368-cru.h | 39 #define SCLK_UART0 77 macro
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| /linux-4.4.14/include/dt-bindings/clock/ |
| D | exynos7-clk.h | 82 #define SCLK_UART0 2 macro
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| D | s5pv210.h | 200 #define SCLK_UART0 175 macro
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| D | rk3188-cru-common.h | 29 #define SCLK_UART0 64 macro
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| D | rk3368-cru.h | 39 #define SCLK_UART0 77 macro
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| D | rk3288-cru.h | 41 #define SCLK_UART0 77 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | exynos7-clk.h | 82 #define SCLK_UART0 2 macro
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| D | s5pv210.h | 200 #define SCLK_UART0 175 macro
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| D | rk3188-cru-common.h | 29 #define SCLK_UART0 64 macro
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| D | rk3368-cru.h | 39 #define SCLK_UART0 77 macro
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| D | rk3288-cru.h | 41 #define SCLK_UART0 77 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | exynos7-clk.h | 82 #define SCLK_UART0 2 macro
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| D | s5pv210.h | 200 #define SCLK_UART0 175 macro
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| D | rk3188-cru-common.h | 29 #define SCLK_UART0 64 macro
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| D | rk3368-cru.h | 39 #define SCLK_UART0 77 macro
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| D | rk3288-cru.h | 41 #define SCLK_UART0 77 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | exynos7-clk.h | 82 #define SCLK_UART0 2 macro
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| D | s5pv210.h | 200 #define SCLK_UART0 175 macro
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| D | rk3188-cru-common.h | 29 #define SCLK_UART0 64 macro
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| D | rk3288-cru.h | 41 #define SCLK_UART0 77 macro
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| D | rk3368-cru.h | 39 #define SCLK_UART0 77 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | exynos7-clk.h | 82 #define SCLK_UART0 2 macro
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| D | s5pv210.h | 200 #define SCLK_UART0 175 macro
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| D | rk3188-cru-common.h | 29 #define SCLK_UART0 64 macro
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| D | rk3288-cru.h | 41 #define SCLK_UART0 77 macro
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| D | rk3368-cru.h | 39 #define SCLK_UART0 77 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | exynos7-clk.h | 82 #define SCLK_UART0 2 macro
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| D | s5pv210.h | 200 #define SCLK_UART0 175 macro
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| D | rk3188-cru-common.h | 29 #define SCLK_UART0 64 macro
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| D | rk3288-cru.h | 41 #define SCLK_UART0 77 macro
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| D | rk3368-cru.h | 39 #define SCLK_UART0 77 macro
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| /linux-4.4.14/Documentation/devicetree/bindings/clock/ |
| D | rockchip,rk3288-cru.txt | 60 clocks = <&cru SCLK_UART0>;
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| D | rockchip,rk3188-cru.txt | 60 clocks = <&cru SCLK_UART0>;
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| D | rockchip,rk3368-cru.txt | 60 clocks = <&cru SCLK_UART0>;
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| D | samsung,s5pv210-clock.txt | 76 <&clocks SCLK_UART0>;
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| /linux-4.4.14/arch/arm64/boot/dts/exynos/ |
| D | exynos7.dtsi | 194 <&clock_peric0 SCLK_UART0>;
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | rk3xxx.dtsi | 154 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| D | rk3288-veyron.dtsi | 385 assigned-clocks = <&cru SCLK_UART0>;
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| D | s5pv210.dtsi | 337 <&clocks SCLK_UART0>;
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| D | rk3288.dtsi | 384 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-s5pv210.c | 641 GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
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| D | clk-exynos7.c | 671 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
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| /linux-4.4.14/drivers/clk/rockchip/ |
| D | clk-rk3188.c | 391 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
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| D | clk-rk3368.c | 566 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3288.c | 542 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| /linux-4.4.14/arch/arm64/boot/dts/rockchip/ |
| D | rk3368.dtsi | 363 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|