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Searched refs:SDMA1_REGISTER_OFFSET (Results 1 – 14 of 14) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Dcik_sdma.c74 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_rptr()
98 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_wptr()
119 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_set_wptr()
263 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
313 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
345 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_enable()
380 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_resume()
493 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()
495 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); in cik_sdma_load_microcode()
496 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode()
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Dcik.c167 case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): in cik_get_allowed_info_register()
3743 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
5227 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
5284 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
5373 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
5375 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5574 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5576 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5943 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5944 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
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Dradeon_kfd.c464 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_base_addr()
Dcikd.h1955 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c48 SDMA1_REGISTER_OFFSET
890 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
897 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
900 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
915 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
918 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
925 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
928 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
1129 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset()
1131 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
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Dvi.c403 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
562 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in vi_print_gpu_status_regs()
659 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in vi_gpu_check_soft_reset()
741 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in vi_gpu_soft_reset()
743 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in vi_gpu_soft_reset()
890 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in vi_gpu_pci_config_reset()
892 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in vi_gpu_pci_config_reset()
Dsdma_v2_4.c58 SDMA1_REGISTER_OFFSET
1143 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
1145 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
1200 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1202 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1205 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1207 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
Dsdma_v3_0.c63 SDMA1_REGISTER_OFFSET
1305 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_soft_reset()
1307 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v3_0_soft_reset()
1362 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1364 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1367 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1369 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
Dcik.c1050 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
1107 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in amdgpu_cik_gpu_check_soft_reset()
1194 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
1196 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
1398 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
1400 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
Dvid.h27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
Dcikd.h482 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
Damdgpu_amdkfd_gfx_v7.c284 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_base_addr()
Dgfx_v8_0.c2904 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, in gfx_v8_0_gpu_init()
4169 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); in gfx_v8_0_print_status()
Dgfx_v7_0.c2233 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in gfx_v7_0_gpu_init()
5016 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); in gfx_v7_0_print_status()