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Searched refs:crtc_offsets (Results 1 – 7 of 7) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Drv515.c43 static const u32 crtc_offsets[2] = variable
308 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; in rv515_mc_stop()
311 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
314 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
316 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
317 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
328 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
329 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
331 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
332 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
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Devergreen.c107 static const u32 crtc_offsets[6] = variable
1345 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1355 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1356 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1379 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
2767 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2771 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2774 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2776 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2777 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
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Drs600.c50 static const u32 crtc_offsets[2] = variable
58 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
68 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
69 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
92 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
Dr600.c94 static const u32 crtc_offsets[2] = variable
1586 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()
1587 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1595 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Ddce_v11_0.c46 static const u32 crtc_offsets[] = variable
184 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & in dce_v11_0_is_in_vblank()
195 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_is_counter_moving()
196 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_is_counter_moving()
219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v11_0_vblank_wait()
245 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v11_0_vblank_get_counter()
297 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
298 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
524 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
526 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v11_0_is_display_hung()
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Ddce_v10_0.c46 static const u32 crtc_offsets[] = variable
194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & in dce_v10_0_is_in_vblank()
205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_is_counter_moving()
206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_is_counter_moving()
229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v10_0_vblank_wait()
255 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v10_0_vblank_get_counter()
307 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
308 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
538 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v10_0_is_display_hung()
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Ddce_v8_0.c49 static const u32 crtc_offsets[6] = variable
143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & in dce_v8_0_is_in_vblank()
154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v8_0_is_counter_moving()
155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v8_0_is_counter_moving()
178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v8_0_vblank_wait()
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v8_0_vblank_get_counter()
256 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
257 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
485 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { in dce_v8_0_is_display_hung()
486 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v8_0_is_display_hung()
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