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Searched refs:mmDC_HPD_INT_CONTROL (Results 1 – 4 of 4) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Ddce_v11_0.c386 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); in dce_v11_0_hpd_set_polarity()
391 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); in dce_v11_0_hpd_set_polarity()
3227 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3229 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3232 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3234 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3377 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack()
3379 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_int_ack()
Ddce_v10_0.c396 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); in dce_v10_0_hpd_set_polarity()
401 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); in dce_v10_0_hpd_set_polarity()
3234 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3236 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3239 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3241 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3384 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3386 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_11_0_d.h7272 #define mmDC_HPD_INT_CONTROL 0x1899 macro
Ddce_10_0_d.h7088 #define mmDC_HPD_INT_CONTROL 0x1899 macro