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Searched refs:nvkm_wo32 (Results 1 – 50 of 50) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv25.c41 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); in nv25_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); in nv25_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x049c, 0x00000101); in nv25_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x04b0, 0x00000111); in nv25_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x04c8, 0x00000080); in nv25_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); in nv25_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x04d0, 0x00000001); in nv25_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x04e4, 0x44400000); in nv25_gr_chan_new()
[all …]
Dnv34.c41 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv34_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv34_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv34_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv34_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv34_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv34_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x0480, 0xffff0000); in nv34_gr_chan_new()
51 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv34_gr_chan_new()
[all …]
Dnv35.c41 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv35_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv35_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv35_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv35_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv35_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv35_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x0488, 0xffff0000); in nv35_gr_chan_new()
51 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv35_gr_chan_new()
[all …]
Dnv2a.c41 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv2a_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv2a_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv2a_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv2a_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv2a_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0490, 0x00000111); in nv2a_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x04a8, 0x44400000); in nv2a_gr_chan_new()
49 nvkm_wo32(chan->inst, i, 0x00030303); in nv2a_gr_chan_new()
51 nvkm_wo32(chan->inst, i, 0x00080000); in nv2a_gr_chan_new()
53 nvkm_wo32(chan->inst, i, 0x01012000); in nv2a_gr_chan_new()
[all …]
Dnv30.c42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0428, 0x00000060); in nv30_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0444, 0x00000080); in nv30_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); in nv30_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x044c, 0x00000001); in nv30_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x0460, 0x44400000); in nv30_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x048c, 0xffff0000); in nv30_gr_chan_new()
52 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv30_gr_chan_new()
[all …]
Dnv20.c23 nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4); in nv20_gr_chan_init()
53 nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); in nv20_gr_chan_fini()
95 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv20_gr_chan_new()
96 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv20_gr_chan_new()
97 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv20_gr_chan_new()
98 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv20_gr_chan_new()
99 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv20_gr_chan_new()
100 nvkm_wo32(chan->inst, 0x0490, 0x00000111); in nv20_gr_chan_new()
101 nvkm_wo32(chan->inst, 0x04a8, 0x44400000); in nv20_gr_chan_new()
103 nvkm_wo32(chan->inst, i, 0x00030303); in nv20_gr_chan_new()
[all …]
Dctxgf100.c1294 nvkm_wo32(chan, 0x0200, lower_32_bits(addr + 0x1000)); in gf100_grctx_generate()
1295 nvkm_wo32(chan, 0x0204, upper_32_bits(addr + 0x1000)); in gf100_grctx_generate()
1296 nvkm_wo32(chan, 0x0208, 0xffffffff); in gf100_grctx_generate()
1297 nvkm_wo32(chan, 0x020c, 0x000000ff); in gf100_grctx_generate()
1300 nvkm_wo32(chan, 0x1000, 0x00000000); in gf100_grctx_generate()
1301 nvkm_wo32(chan, 0x1004, 0x00000001 | (addr + 0x2000) >> 8); in gf100_grctx_generate()
1306 nvkm_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); in gf100_grctx_generate()
1307 nvkm_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); in gf100_grctx_generate()
1311 nvkm_wo32(chan, 0x0210, 0x00080004); in gf100_grctx_generate()
1312 nvkm_wo32(chan, 0x0214, 0x00000000); in gf100_grctx_generate()
[all …]
Dnv40.c51 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv40_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv40_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv40_gr_object_bind()
57 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv40_gr_object_bind()
58 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in nv40_gr_object_bind()
85 nvkm_wo32(*pgpuobj, 0x00000, chan->inst >> 4); in nv40_gr_chan_bind()
Dgf100.c294 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); in gf100_gr_chan_bind()
297 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); in gf100_gr_chan_bind()
298 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma.offset >> 8); in gf100_gr_chan_bind()
300 nvkm_wo32(*pgpuobj, 0xf4, 0); in gf100_gr_chan_bind()
301 nvkm_wo32(*pgpuobj, 0xf8, 0); in gf100_gr_chan_bind()
302 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); in gf100_gr_chan_bind()
303 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma.offset)); in gf100_gr_chan_bind()
304 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma.offset)); in gf100_gr_chan_bind()
305 nvkm_wo32(*pgpuobj, 0x1c, 1); in gf100_gr_chan_bind()
306 nvkm_wo32(*pgpuobj, 0x20, 0); in gf100_gr_chan_bind()
[all …]
Dnv50.c48 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
49 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
Dctxnv40.c585 nvkm_wo32(obj, offset * 4, 0x3f800000); in nv40_gr_construct_shader()
589 nvkm_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); in nv40_gr_construct_shader()
591 nvkm_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); in nv40_gr_construct_shader()
Dctxnv40.h128 nvkm_wo32(ctx->data, reg * 4, val); in gr_def()
Dnv04.c1050 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv04_gr_object_bind()
1054 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv04_gr_object_bind()
1055 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv04_gr_object_bind()
1056 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv04_gr_object_bind()
Dctxnv50.c788 nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); in dd_emit()
1161 nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); in xf_emit()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Ddmag84.c67 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); in g84_fifo_dma_new()
68 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in g84_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); in g84_fifo_dma_new()
70 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); in g84_fifo_dma_new()
71 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); in g84_fifo_dma_new()
72 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in g84_fifo_dma_new()
73 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in g84_fifo_dma_new()
74 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); in g84_fifo_dma_new()
75 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in g84_fifo_dma_new()
76 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in g84_fifo_dma_new()
[all …]
Ddmanv50.c67 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
68 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
70 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
71 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); in nv50_fifo_dma_new()
72 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in nv50_fifo_dma_new()
73 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in nv50_fifo_dma_new()
74 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); in nv50_fifo_dma_new()
75 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in nv50_fifo_dma_new()
76 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in nv50_fifo_dma_new()
[all …]
Dgpfifogf100.c76 nvkm_wo32(inst, offset + 0x00, 0x00000000); in gf100_fifo_gpfifo_engine_fini()
77 nvkm_wo32(inst, offset + 0x04, 0x00000000); in gf100_fifo_gpfifo_engine_fini()
95 nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4); in gf100_fifo_gpfifo_engine_init()
96 nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); in gf100_fifo_gpfifo_engine_init()
242 nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr)); in gf100_fifo_gpfifo_new()
243 nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr)); in gf100_fifo_gpfifo_new()
244 nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff); in gf100_fifo_gpfifo_new()
245 nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff); in gf100_fifo_gpfifo_new()
260 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); in gf100_fifo_gpfifo_new()
266 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); in gf100_fifo_gpfifo_new()
[all …]
Dgpfifog84.c71 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in g84_fifo_gpfifo_new()
72 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in g84_fifo_gpfifo_new()
73 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in g84_fifo_gpfifo_new()
74 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); in g84_fifo_gpfifo_new()
75 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); in g84_fifo_gpfifo_new()
76 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in g84_fifo_gpfifo_new()
77 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in g84_fifo_gpfifo_new()
78 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); in g84_fifo_gpfifo_new()
79 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | in g84_fifo_gpfifo_new()
82 nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); in g84_fifo_gpfifo_new()
[all …]
Dgpfifogk104.c89 nvkm_wo32(inst, offset + 0x00, 0x00000000); in gk104_fifo_gpfifo_engine_fini()
90 nvkm_wo32(inst, offset + 0x04, 0x00000000); in gk104_fifo_gpfifo_engine_fini()
108 nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4); in gk104_fifo_gpfifo_engine_init()
109 nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); in gk104_fifo_gpfifo_engine_init()
275 nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr)); in gk104_fifo_gpfifo_new()
276 nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr)); in gk104_fifo_gpfifo_new()
277 nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff); in gk104_fifo_gpfifo_new()
278 nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff); in gk104_fifo_gpfifo_new()
292 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); in gk104_fifo_gpfifo_new()
298 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); in gk104_fifo_gpfifo_new()
[all …]
Dgpfifonv50.c71 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in nv50_fifo_gpfifo_new()
72 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in nv50_fifo_gpfifo_new()
73 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in nv50_fifo_gpfifo_new()
74 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); in nv50_fifo_gpfifo_new()
75 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); in nv50_fifo_gpfifo_new()
76 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in nv50_fifo_gpfifo_new()
77 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in nv50_fifo_gpfifo_new()
78 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); in nv50_fifo_gpfifo_new()
79 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | in nv50_fifo_gpfifo_new()
Dchang84.c121 nvkm_wo32(chan->eng, offset + 0x00, 0x00000000); in g84_fifo_chan_engine_fini()
122 nvkm_wo32(chan->eng, offset + 0x04, 0x00000000); in g84_fifo_chan_engine_fini()
123 nvkm_wo32(chan->eng, offset + 0x08, 0x00000000); in g84_fifo_chan_engine_fini()
124 nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000); in g84_fifo_chan_engine_fini()
125 nvkm_wo32(chan->eng, offset + 0x10, 0x00000000); in g84_fifo_chan_engine_fini()
126 nvkm_wo32(chan->eng, offset + 0x14, 0x00000000); in g84_fifo_chan_engine_fini()
148 nvkm_wo32(chan->eng, offset + 0x00, 0x00190000); in g84_fifo_chan_engine_init()
149 nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit)); in g84_fifo_chan_engine_init()
150 nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start)); in g84_fifo_chan_engine_init()
151 nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 | in g84_fifo_chan_engine_init()
[all …]
Dchannv50.c89 nvkm_wo32(chan->eng, offset + 0x00, 0x00000000); in nv50_fifo_chan_engine_fini()
90 nvkm_wo32(chan->eng, offset + 0x04, 0x00000000); in nv50_fifo_chan_engine_fini()
91 nvkm_wo32(chan->eng, offset + 0x08, 0x00000000); in nv50_fifo_chan_engine_fini()
92 nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000); in nv50_fifo_chan_engine_fini()
93 nvkm_wo32(chan->eng, offset + 0x10, 0x00000000); in nv50_fifo_chan_engine_fini()
94 nvkm_wo32(chan->eng, offset + 0x14, 0x00000000); in nv50_fifo_chan_engine_fini()
117 nvkm_wo32(chan->eng, offset + 0x00, 0x00190000); in nv50_fifo_chan_engine_init()
118 nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit)); in nv50_fifo_chan_engine_init()
119 nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start)); in nv50_fifo_chan_engine_init()
120 nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 | in nv50_fifo_chan_engine_init()
[all …]
Ddmanv10.c76 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv10_fifo_dma_new()
77 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv10_fifo_dma_new()
78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); in nv10_fifo_dma_new()
79 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, in nv10_fifo_dma_new()
Ddmanv17.c77 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv17_fifo_dma_new()
78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv17_fifo_dma_new()
79 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); in nv17_fifo_dma_new()
80 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, in nv17_fifo_dma_new()
Ddmanv40.c77 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); in nv40_fifo_dma_engine_fini()
108 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst); in nv40_fifo_dma_engine_init()
222 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv40_fifo_dma_new()
223 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv40_fifo_dma_new()
224 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); in nv40_fifo_dma_new()
225 nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 | in nv40_fifo_dma_new()
232 nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff); in nv40_fifo_dma_new()
Ddmanv04.c99 nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); in nv04_fifo_dma_fini()
143 nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000); in nv04_fifo_dma_dtor()
200 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv04_fifo_dma_new()
201 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv04_fifo_dma_new()
202 nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4); in nv04_fifo_dma_new()
203 nvkm_wo32(imem->ramfc, chan->ramfc + 0x10, in nv04_fifo_dma_new()
Dnv50.c42 nvkm_wo32(cur, p++ * 4, i); in nv50_fifo_runlist_update_locked()
Dgf100.c64 nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid); in gf100_fifo_runlist_update()
65 nvkm_wo32(cur, (nr * 8) + 4, 0x00000004); in gf100_fifo_runlist_update()
Dgk104.c65 nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid); in gk104_fifo_runlist_update()
66 nvkm_wo32(cur, (nr * 8) + 4, 0x00000000); in gk104_fifo_runlist_update()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv44.c77 nvkm_wo32(pgt, base + 0x0, tmp[0]); in nv44_vm_fill()
78 nvkm_wo32(pgt, base + 0x4, tmp[1]); in nv44_vm_fill()
79 nvkm_wo32(pgt, base + 0x8, tmp[2]); in nv44_vm_fill()
80 nvkm_wo32(pgt, base + 0xc, tmp[3] | 0x40000000); in nv44_vm_fill()
104 nvkm_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27); in nv44_vm_map_sg()
105 nvkm_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22); in nv44_vm_map_sg()
106 nvkm_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17); in nv44_vm_map_sg()
107 nvkm_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000); in nv44_vm_map_sg()
131 nvkm_wo32(pgt, pte++ * 4, 0x00000000); in nv44_vm_unmap()
132 nvkm_wo32(pgt, pte++ * 4, 0x00000000); in nv44_vm_unmap()
[all …]
Dgf100.c83 nvkm_wo32(pgd, (index * 8) + 0, pde[0]); in gf100_vm_map_pgt()
84 nvkm_wo32(pgd, (index * 8) + 4, pde[1]); in gf100_vm_map_pgt()
121 nvkm_wo32(pgt, pte + 0, lower_32_bits(phys)); in gf100_vm_map()
122 nvkm_wo32(pgt, pte + 4, upper_32_bits(phys)); in gf100_vm_map()
141 nvkm_wo32(pgt, pte + 0, lower_32_bits(phys)); in gf100_vm_map_sg()
142 nvkm_wo32(pgt, pte + 4, upper_32_bits(phys)); in gf100_vm_map_sg()
154 nvkm_wo32(pgt, pte + 0, 0x00000000); in gf100_vm_unmap()
155 nvkm_wo32(pgt, pte + 4, 0x00000000); in gf100_vm_unmap()
Dnv50.c58 nvkm_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); in nv50_vm_map_pgt()
59 nvkm_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); in nv50_vm_map_pgt()
117 nvkm_wo32(pgt, pte + 0, offset_l); in nv50_vm_map()
118 nvkm_wo32(pgt, pte + 4, offset_h); in nv50_vm_map()
135 nvkm_wo32(pgt, pte + 0, lower_32_bits(phys)); in nv50_vm_map_sg()
136 nvkm_wo32(pgt, pte + 4, upper_32_bits(phys)); in nv50_vm_map_sg()
148 nvkm_wo32(pgt, pte + 0, 0x00000000); in nv50_vm_unmap()
149 nvkm_wo32(pgt, pte + 4, 0x00000000); in nv50_vm_unmap()
Dnv04.c45 nvkm_wo32(pgt, pte, phys | 3); in nv04_vm_map_sg()
60 nvkm_wo32(pgt, pte, 0x00000000); in nv04_vm_unmap()
97 nvkm_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ in nv04_mmu_oneinit()
98 nvkm_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1); in nv04_mmu_oneinit()
Dnv41.c47 nvkm_wo32(pgt, pte, (phys >> 7) | 1); in nv41_vm_map_sg()
62 nvkm_wo32(pgt, pte, 0x00000000); in nv41_vm_unmap()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dnv50.c107 nvkm_wo32(bar->bar3, 0x00, 0x7fc00000); in nv50_bar_oneinit()
108 nvkm_wo32(bar->bar3, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
109 nvkm_wo32(bar->bar3, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
110 nvkm_wo32(bar->bar3, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
112 nvkm_wo32(bar->bar3, 0x10, 0x00000000); in nv50_bar_oneinit()
113 nvkm_wo32(bar->bar3, 0x14, 0x00000000); in nv50_bar_oneinit()
136 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000); in nv50_bar_oneinit()
137 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
138 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
139 nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
[all …]
Dgf100.c86 nvkm_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); in gf100_bar_ctor_vm()
87 nvkm_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); in gf100_bar_ctor_vm()
88 nvkm_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); in gf100_bar_ctor_vm()
89 nvkm_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); in gf100_bar_ctor_vm()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/dma/
Dusergf119.c50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gf119_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8); in gf119_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8); in gf119_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in gf119_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in gf119_dmaobj_bind()
55 nvkm_wo32(*pgpuobj, 0x14, 0x00000000); in gf119_dmaobj_bind()
Dusergf100.c51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gf100_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); in gf100_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); in gf100_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | in gf100_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in gf100_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); in gf100_dmaobj_bind()
Dusernv50.c51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in nv50_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); in nv50_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); in nv50_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | in nv50_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in nv50_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); in nv50_dmaobj_bind()
Dusernv04.c65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); in nv04_dmaobj_bind()
66 nvkm_wo32(*pgpuobj, 0x04, length); in nv04_dmaobj_bind()
67 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
68 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c41 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in g84_cipher_oclass_bind()
42 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in g84_cipher_oclass_bind()
43 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in g84_cipher_oclass_bind()
44 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in g84_cipher_oclass_bind()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv31.c46 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv31_mpeg_object_bind()
47 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv31_mpeg_object_bind()
48 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv31_mpeg_object_bind()
49 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv31_mpeg_object_bind()
Dnv50.c43 nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1); in nv50_mpeg_cclass_bind()
44 nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c); in nv50_mpeg_cclass_bind()
Dnv44.c61 nvkm_wo32(*pgpuobj, 0x78, 0x02001ec1); in nv44_mpeg_chan_bind()
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/core/
Dmemory.h46 #define nvkm_wo32(o,a,d) (o)->func->wr32((o), (a), (d)) macro
49 nvkm_wo32((o), _addr, (_data & ~(m)) | (d)); \
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/core/
Dgpuobj.c54 nvkm_wo32(gpuobj->memory, offset, data); in nvkm_gpuobj_heap_wr32()
105 nvkm_wo32(gpuobj->parent, gpuobj->node->offset + offset, data); in nvkm_gpuobj_wr32()
174 nvkm_wo32(gpuobj, offset, 0x00000000); in nvkm_gpuobj_ctor()
Dramht.c92 nvkm_wo32(ramht->gpuobj, (co << 3) + 0, handle); in nvkm_ramht_update()
93 nvkm_wo32(ramht->gpuobj, (co << 3) + 4, context); in nvkm_ramht_update()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dbase.c156 return nvkm_wo32(iobj->parent, offset, data); in nvkm_instobj_wr32_slow()
205 nvkm_wo32(memory, offset, 0x00000000); in nvkm_instobj_new()
283 nvkm_wo32(memory, i, iobj->suspend[i / 4]); in nvkm_instmem_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/
Dxtensa.c132 nvkm_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); in nvkm_xtensa_init()
Dfalcon.c255 nvkm_wo32(falcon->core, i, falcon->code.data[i / 4]); in nvkm_falcon_init()