| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | ni_dma.c | 159 u32 rb_cntl; in cayman_dma_stop() local
166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
167 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
171 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
172 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
173 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
190 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local
211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
213 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in cayman_dma_resume()
[all …]
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| D | r600_dma.c | 101 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() local
106 rb_cntl &= ~DMA_RB_ENABLE; in r600_dma_stop()
107 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
123 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local
132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
134 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in r600_dma_resume()
136 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
149 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in r600_dma_resume()
170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
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| D | cik_sdma.c | 252 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
265 rb_cntl &= ~SDMA_RB_ENABLE; in cik_sdma_gfx_stop()
266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
368 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
391 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; in cik_sdma_gfx_resume()
393 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
406 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; in cik_sdma_gfx_resume()
415 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); in cik_sdma_gfx_resume()
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| D | ni.c | 1695 uint32_t rb_cntl; in cayman_cp_resume() local
1700 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1701 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; in cayman_cp_resume()
1703 rb_cntl |= BUF_SWAP_32BIT; in cayman_cp_resume()
1705 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v2_4.c | 373 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_stop() local
381 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
382 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop()
383 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop()
443 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_resume() local
466 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
467 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
469 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v2_4_gfx_resume()
470 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v2_4_gfx_resume()
473 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_resume()
[all …]
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| D | sdma_v3_0.c | 484 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_stop() local
492 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
493 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop()
494 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop()
579 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_resume() local
603 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
604 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
606 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v3_0_gfx_resume()
607 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v3_0_gfx_resume()
610 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_resume()
[all …]
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| D | cik_sdma.c | 332 u32 rb_cntl; in cik_sdma_gfx_stop() local
340 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
341 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; in cik_sdma_gfx_stop()
342 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop()
400 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
425 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
427 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | in cik_sdma_gfx_resume()
430 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_resume()
442 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; in cik_sdma_gfx_resume()
452 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); in cik_sdma_gfx_resume()
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