1 /*
2 * linux/arch/arm/mach-integrator/integrator_ap.c
3 *
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/io.h>
31 #include <linux/irqchip.h>
32 #include <linux/mtd/physmap.h>
33 #include <linux/platform_data/clk-integrator.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_address.h>
36 #include <linux/of_platform.h>
37 #include <linux/stat.h>
38 #include <linux/termios.h>
39
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/setup.h>
42 #include <asm/param.h> /* HZ */
43 #include <asm/mach-types.h>
44
45 #include <asm/mach/arch.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/map.h>
48 #include <asm/mach/time.h>
49
50 #include "hardware.h"
51 #include "cm.h"
52 #include "common.h"
53 #include "pci_v3.h"
54 #include "lm.h"
55
56 /* Base address to the AP system controller */
57 void __iomem *ap_syscon_base;
58 /* Base address to the external bus interface */
59 static void __iomem *ebi_base;
60
61
62 /*
63 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
64 * is the (PA >> 12).
65 *
66 * Setup a VA for the Integrator interrupt controller (for header #0,
67 * just for now).
68 */
69 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
70
71 /*
72 * Logical Physical
73 * ef000000 Cache flush
74 * f1100000 11000000 System controller registers
75 * f1300000 13000000 Counter/Timer
76 * f1400000 14000000 Interrupt controller
77 * f1600000 16000000 UART 0
78 * f1700000 17000000 UART 1
79 * f1a00000 1a000000 Debug LEDs
80 * f1b00000 1b000000 GPIO
81 */
82
83 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
84 {
85 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
86 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
87 .length = SZ_4K,
88 .type = MT_DEVICE
89 }, {
90 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
91 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
92 .length = SZ_4K,
93 .type = MT_DEVICE
94 }, {
95 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
96 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
97 .length = SZ_4K,
98 .type = MT_DEVICE
99 }, {
100 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
101 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
102 .length = SZ_4K,
103 .type = MT_DEVICE
104 }
105 };
106
ap_map_io(void)107 static void __init ap_map_io(void)
108 {
109 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
110 pci_v3_early_init();
111 }
112
113 #ifdef CONFIG_PM
114 static unsigned long ic_irq_enable;
115
irq_suspend(void)116 static int irq_suspend(void)
117 {
118 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
119 return 0;
120 }
121
irq_resume(void)122 static void irq_resume(void)
123 {
124 /* disable all irq sources */
125 cm_clear_irqs();
126 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
127 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
128
129 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
130 }
131 #else
132 #define irq_suspend NULL
133 #define irq_resume NULL
134 #endif
135
136 static struct syscore_ops irq_syscore_ops = {
137 .suspend = irq_suspend,
138 .resume = irq_resume,
139 };
140
irq_syscore_init(void)141 static int __init irq_syscore_init(void)
142 {
143 register_syscore_ops(&irq_syscore_ops);
144
145 return 0;
146 }
147
148 device_initcall(irq_syscore_init);
149
150 /*
151 * Flash handling.
152 */
ap_flash_init(struct platform_device * dev)153 static int ap_flash_init(struct platform_device *dev)
154 {
155 u32 tmp;
156
157 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
158 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
159
160 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
161 INTEGRATOR_EBI_WRITE_ENABLE;
162 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
163
164 if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
165 & INTEGRATOR_EBI_WRITE_ENABLE)) {
166 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
167 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
168 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
169 }
170 return 0;
171 }
172
ap_flash_exit(struct platform_device * dev)173 static void ap_flash_exit(struct platform_device *dev)
174 {
175 u32 tmp;
176
177 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
178 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
179
180 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
181 ~INTEGRATOR_EBI_WRITE_ENABLE;
182 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
183
184 if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
185 INTEGRATOR_EBI_WRITE_ENABLE) {
186 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
187 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
188 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
189 }
190 }
191
ap_flash_set_vpp(struct platform_device * pdev,int on)192 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
193 {
194 if (on)
195 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
196 ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
197 else
198 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
199 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
200 }
201
202 static struct physmap_flash_data ap_flash_data = {
203 .width = 4,
204 .init = ap_flash_init,
205 .exit = ap_flash_exit,
206 .set_vpp = ap_flash_set_vpp,
207 };
208
209 /*
210 * For the PL010 found in the Integrator/AP some of the UART control is
211 * implemented in the system controller and accessed using a callback
212 * from the driver.
213 */
integrator_uart_set_mctrl(struct amba_device * dev,void __iomem * base,unsigned int mctrl)214 static void integrator_uart_set_mctrl(struct amba_device *dev,
215 void __iomem *base, unsigned int mctrl)
216 {
217 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
218 u32 phybase = dev->res.start;
219
220 if (phybase == INTEGRATOR_UART0_BASE) {
221 /* UART0 */
222 rts_mask = 1 << 4;
223 dtr_mask = 1 << 5;
224 } else {
225 /* UART1 */
226 rts_mask = 1 << 6;
227 dtr_mask = 1 << 7;
228 }
229
230 if (mctrl & TIOCM_RTS)
231 ctrlc |= rts_mask;
232 else
233 ctrls |= rts_mask;
234
235 if (mctrl & TIOCM_DTR)
236 ctrlc |= dtr_mask;
237 else
238 ctrls |= dtr_mask;
239
240 __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
241 __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
242 }
243
244 struct amba_pl010_data ap_uart_data = {
245 .set_mctrl = integrator_uart_set_mctrl,
246 };
247
ap_init_early(void)248 void __init ap_init_early(void)
249 {
250 }
251
ap_init_irq_of(void)252 static void __init ap_init_irq_of(void)
253 {
254 cm_init();
255 irqchip_init();
256 }
257
258 /* For the Device Tree, add in the UART callbacks as AUXDATA */
259 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
260 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
261 "rtc", NULL),
262 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
263 "uart0", &ap_uart_data),
264 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
265 "uart1", &ap_uart_data),
266 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
267 "kmi0", NULL),
268 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
269 "kmi1", NULL),
270 OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
271 "physmap-flash", &ap_flash_data),
272 { /* sentinel */ },
273 };
274
275 static const struct of_device_id ap_syscon_match[] = {
276 { .compatible = "arm,integrator-ap-syscon"},
277 { },
278 };
279
280 static const struct of_device_id ebi_match[] = {
281 { .compatible = "arm,external-bus-interface"},
282 { },
283 };
284
ap_init_of(void)285 static void __init ap_init_of(void)
286 {
287 unsigned long sc_dec;
288 struct device_node *syscon;
289 struct device_node *ebi;
290 int i;
291
292 syscon = of_find_matching_node(NULL, ap_syscon_match);
293 if (!syscon)
294 return;
295 ebi = of_find_matching_node(NULL, ebi_match);
296 if (!ebi)
297 return;
298
299 ap_syscon_base = of_iomap(syscon, 0);
300 if (!ap_syscon_base)
301 return;
302 ebi_base = of_iomap(ebi, 0);
303 if (!ebi_base)
304 return;
305
306 of_platform_populate(NULL, of_default_bus_match_table,
307 ap_auxdata_lookup, NULL);
308
309 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
310 for (i = 0; i < 4; i++) {
311 struct lm_device *lmdev;
312
313 if ((sc_dec & (16 << i)) == 0)
314 continue;
315
316 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
317 if (!lmdev)
318 continue;
319
320 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
321 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
322 lmdev->resource.flags = IORESOURCE_MEM;
323 lmdev->irq = irq_of_parse_and_map(syscon, i);
324 lmdev->id = i;
325
326 lm_device_register(lmdev);
327 }
328 }
329
330 static const char * ap_dt_board_compat[] = {
331 "arm,integrator-ap",
332 NULL,
333 };
334
335 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
336 .reserve = integrator_reserve,
337 .map_io = ap_map_io,
338 .init_early = ap_init_early,
339 .init_irq = ap_init_irq_of,
340 .init_machine = ap_init_of,
341 .dt_compat = ap_dt_board_compat,
342 MACHINE_END
343