1 /*
2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
3 *
4 * lirc_sir - Device driver for use with SIR (serial infra red)
5 * mode of IrDA on many notebooks.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 *
22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
23 * added timeout and relaxed pulse detection, removed gap bug
24 *
25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
26 * added support for Tekram Irmate 210 (sending does not work yet,
27 * kind of disappointing that nobody was able to implement that
28 * before),
29 * major clean-up
30 *
31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
32 * added support for StrongARM SA1100 embedded microprocessor
33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
34 */
35
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38 #include <linux/module.h>
39 #include <linux/sched.h>
40 #include <linux/errno.h>
41 #include <linux/signal.h>
42 #include <linux/fs.h>
43 #include <linux/interrupt.h>
44 #include <linux/ioport.h>
45 #include <linux/kernel.h>
46 #include <linux/serial_reg.h>
47 #include <linux/time.h>
48 #include <linux/string.h>
49 #include <linux/types.h>
50 #include <linux/wait.h>
51 #include <linux/mm.h>
52 #include <linux/delay.h>
53 #include <linux/poll.h>
54 #include <linux/io.h>
55 #include <asm/irq.h>
56 #include <linux/fcntl.h>
57 #include <linux/platform_device.h>
58
59 #include <linux/timer.h>
60
61 #include <media/lirc.h>
62 #include <media/lirc_dev.h>
63
64 /* SECTION: Definitions */
65
66 /*** Tekram dongle ***/
67 #ifdef LIRC_SIR_TEKRAM
68 /* stolen from kernel source */
69 /* definitions for Tekram dongle */
70 #define TEKRAM_115200 0x00
71 #define TEKRAM_57600 0x01
72 #define TEKRAM_38400 0x02
73 #define TEKRAM_19200 0x03
74 #define TEKRAM_9600 0x04
75 #define TEKRAM_2400 0x08
76
77 #define TEKRAM_PW 0x10 /* Pulse select bit */
78
79 /* 10bit * 1s/115200bit in milliseconds = 87ms*/
80 #define TIME_CONST (10000000ul/115200ul)
81
82 #endif
83
84 #ifdef LIRC_SIR_ACTISYS_ACT200L
85 static void init_act200(void);
86 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
87 static void init_act220(void);
88 #endif
89
90 #define RBUF_LEN 1024
91 #define WBUF_LEN 1024
92
93 #define LIRC_DRIVER_NAME "lirc_sir"
94
95 #define PULSE '['
96
97 #ifndef LIRC_SIR_TEKRAM
98 /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
99 #define TIME_CONST (9000000ul/115200ul)
100 #endif
101
102
103 /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
104 #define SIR_TIMEOUT (HZ*5/100)
105
106 #ifndef LIRC_ON_SA1100
107 #ifndef LIRC_IRQ
108 #define LIRC_IRQ 4
109 #endif
110 #ifndef LIRC_PORT
111 /* for external dongles, default to com1 */
112 #if defined(LIRC_SIR_ACTISYS_ACT200L) || \
113 defined(LIRC_SIR_ACTISYS_ACT220L) || \
114 defined(LIRC_SIR_TEKRAM)
115 #define LIRC_PORT 0x3f8
116 #else
117 /* onboard sir ports are typically com3 */
118 #define LIRC_PORT 0x3e8
119 #endif
120 #endif
121
122 static int io = LIRC_PORT;
123 static int irq = LIRC_IRQ;
124 static int threshold = 3;
125 #endif
126
127 static DEFINE_SPINLOCK(timer_lock);
128 static struct timer_list timerlist;
129 /* time of last signal change detected */
130 static struct timeval last_tv = {0, 0};
131 /* time of last UART data ready interrupt */
132 static struct timeval last_intr_tv = {0, 0};
133 static int last_value;
134
135 static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
136
137 static DEFINE_SPINLOCK(hardware_lock);
138
139 static int rx_buf[RBUF_LEN];
140 static unsigned int rx_tail, rx_head;
141
142 static bool debug;
143
144 /* SECTION: Prototypes */
145
146 /* Communication with user-space */
147 static unsigned int lirc_poll(struct file *file, poll_table *wait);
148 static ssize_t lirc_read(struct file *file, char __user *buf, size_t count,
149 loff_t *ppos);
150 static ssize_t lirc_write(struct file *file, const char __user *buf, size_t n,
151 loff_t *pos);
152 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
153 static void add_read_queue(int flag, unsigned long val);
154 static int init_chrdev(void);
155 static void drop_chrdev(void);
156 /* Hardware */
157 static irqreturn_t sir_interrupt(int irq, void *dev_id);
158 static void send_space(unsigned long len);
159 static void send_pulse(unsigned long len);
160 static int init_hardware(void);
161 static void drop_hardware(void);
162 /* Initialisation */
163 static int init_port(void);
164 static void drop_port(void);
165
sinp(int offset)166 static inline unsigned int sinp(int offset)
167 {
168 return inb(io + offset);
169 }
170
soutp(int offset,int value)171 static inline void soutp(int offset, int value)
172 {
173 outb(value, io + offset);
174 }
175
176 #ifndef MAX_UDELAY_MS
177 #define MAX_UDELAY_US 5000
178 #else
179 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
180 #endif
181
safe_udelay(unsigned long usecs)182 static void safe_udelay(unsigned long usecs)
183 {
184 while (usecs > MAX_UDELAY_US) {
185 udelay(MAX_UDELAY_US);
186 usecs -= MAX_UDELAY_US;
187 }
188 udelay(usecs);
189 }
190
191 /* SECTION: Communication with user-space */
192
lirc_poll(struct file * file,poll_table * wait)193 static unsigned int lirc_poll(struct file *file, poll_table *wait)
194 {
195 poll_wait(file, &lirc_read_queue, wait);
196 if (rx_head != rx_tail)
197 return POLLIN | POLLRDNORM;
198 return 0;
199 }
200
lirc_read(struct file * file,char __user * buf,size_t count,loff_t * ppos)201 static ssize_t lirc_read(struct file *file, char __user *buf, size_t count,
202 loff_t *ppos)
203 {
204 int n = 0;
205 int retval = 0;
206 DECLARE_WAITQUEUE(wait, current);
207
208 if (count % sizeof(int))
209 return -EINVAL;
210
211 add_wait_queue(&lirc_read_queue, &wait);
212 set_current_state(TASK_INTERRUPTIBLE);
213 while (n < count) {
214 if (rx_head != rx_tail) {
215 if (copy_to_user(buf + n,
216 rx_buf + rx_head,
217 sizeof(int))) {
218 retval = -EFAULT;
219 break;
220 }
221 rx_head = (rx_head + 1) & (RBUF_LEN - 1);
222 n += sizeof(int);
223 } else {
224 if (file->f_flags & O_NONBLOCK) {
225 retval = -EAGAIN;
226 break;
227 }
228 if (signal_pending(current)) {
229 retval = -ERESTARTSYS;
230 break;
231 }
232 schedule();
233 set_current_state(TASK_INTERRUPTIBLE);
234 }
235 }
236 remove_wait_queue(&lirc_read_queue, &wait);
237 set_current_state(TASK_RUNNING);
238 return n ? n : retval;
239 }
lirc_write(struct file * file,const char __user * buf,size_t n,loff_t * pos)240 static ssize_t lirc_write(struct file *file, const char __user *buf, size_t n,
241 loff_t *pos)
242 {
243 unsigned long flags;
244 int i, count;
245 int *tx_buf;
246
247 count = n / sizeof(int);
248 if (n % sizeof(int) || count % 2 == 0)
249 return -EINVAL;
250 tx_buf = memdup_user(buf, n);
251 if (IS_ERR(tx_buf))
252 return PTR_ERR(tx_buf);
253 i = 0;
254 local_irq_save(flags);
255 while (1) {
256 if (i >= count)
257 break;
258 if (tx_buf[i])
259 send_pulse(tx_buf[i]);
260 i++;
261 if (i >= count)
262 break;
263 if (tx_buf[i])
264 send_space(tx_buf[i]);
265 i++;
266 }
267 local_irq_restore(flags);
268 kfree(tx_buf);
269 return count;
270 }
271
lirc_ioctl(struct file * filep,unsigned int cmd,unsigned long arg)272 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
273 {
274 u32 __user *uptr = (u32 __user *)arg;
275 int retval = 0;
276 u32 value = 0;
277
278 if (cmd == LIRC_GET_FEATURES)
279 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
280 else if (cmd == LIRC_GET_SEND_MODE)
281 value = LIRC_MODE_PULSE;
282 else if (cmd == LIRC_GET_REC_MODE)
283 value = LIRC_MODE_MODE2;
284
285 switch (cmd) {
286 case LIRC_GET_FEATURES:
287 case LIRC_GET_SEND_MODE:
288 case LIRC_GET_REC_MODE:
289 retval = put_user(value, uptr);
290 break;
291
292 case LIRC_SET_SEND_MODE:
293 case LIRC_SET_REC_MODE:
294 retval = get_user(value, uptr);
295 break;
296 default:
297 retval = -ENOIOCTLCMD;
298
299 }
300
301 if (retval)
302 return retval;
303 if (cmd == LIRC_SET_REC_MODE) {
304 if (value != LIRC_MODE_MODE2)
305 retval = -ENOSYS;
306 } else if (cmd == LIRC_SET_SEND_MODE) {
307 if (value != LIRC_MODE_PULSE)
308 retval = -ENOSYS;
309 }
310
311 return retval;
312 }
313
add_read_queue(int flag,unsigned long val)314 static void add_read_queue(int flag, unsigned long val)
315 {
316 unsigned int new_rx_tail;
317 int newval;
318
319 pr_debug("add flag %d with val %lu\n", flag, val);
320
321 newval = val & PULSE_MASK;
322
323 /*
324 * statistically, pulses are ~TIME_CONST/2 too long. we could
325 * maybe make this more exact, but this is good enough
326 */
327 if (flag) {
328 /* pulse */
329 if (newval > TIME_CONST/2)
330 newval -= TIME_CONST/2;
331 else /* should not ever happen */
332 newval = 1;
333 newval |= PULSE_BIT;
334 } else {
335 newval += TIME_CONST/2;
336 }
337 new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
338 if (new_rx_tail == rx_head) {
339 pr_debug("Buffer overrun.\n");
340 return;
341 }
342 rx_buf[rx_tail] = newval;
343 rx_tail = new_rx_tail;
344 wake_up_interruptible(&lirc_read_queue);
345 }
346
347 static const struct file_operations lirc_fops = {
348 .owner = THIS_MODULE,
349 .read = lirc_read,
350 .write = lirc_write,
351 .poll = lirc_poll,
352 .unlocked_ioctl = lirc_ioctl,
353 #ifdef CONFIG_COMPAT
354 .compat_ioctl = lirc_ioctl,
355 #endif
356 .open = lirc_dev_fop_open,
357 .release = lirc_dev_fop_close,
358 .llseek = no_llseek,
359 };
360
set_use_inc(void * data)361 static int set_use_inc(void *data)
362 {
363 return 0;
364 }
365
set_use_dec(void * data)366 static void set_use_dec(void *data)
367 {
368 }
369
370 static struct lirc_driver driver = {
371 .name = LIRC_DRIVER_NAME,
372 .minor = -1,
373 .code_length = 1,
374 .sample_rate = 0,
375 .data = NULL,
376 .add_to_buf = NULL,
377 .set_use_inc = set_use_inc,
378 .set_use_dec = set_use_dec,
379 .fops = &lirc_fops,
380 .dev = NULL,
381 .owner = THIS_MODULE,
382 };
383
384 static struct platform_device *lirc_sir_dev;
385
init_chrdev(void)386 static int init_chrdev(void)
387 {
388 driver.dev = &lirc_sir_dev->dev;
389 driver.minor = lirc_register_driver(&driver);
390 if (driver.minor < 0) {
391 pr_err("init_chrdev() failed.\n");
392 return -EIO;
393 }
394 return 0;
395 }
396
drop_chrdev(void)397 static void drop_chrdev(void)
398 {
399 lirc_unregister_driver(driver.minor);
400 }
401
402 /* SECTION: Hardware */
delta(struct timeval * tv1,struct timeval * tv2)403 static long delta(struct timeval *tv1, struct timeval *tv2)
404 {
405 unsigned long deltv;
406
407 deltv = tv2->tv_sec - tv1->tv_sec;
408 if (deltv > 15)
409 deltv = 0xFFFFFF;
410 else
411 deltv = deltv*1000000 +
412 tv2->tv_usec -
413 tv1->tv_usec;
414 return deltv;
415 }
416
sir_timeout(unsigned long data)417 static void sir_timeout(unsigned long data)
418 {
419 /*
420 * if last received signal was a pulse, but receiving stopped
421 * within the 9 bit frame, we need to finish this pulse and
422 * simulate a signal change to from pulse to space. Otherwise
423 * upper layers will receive two sequences next time.
424 */
425
426 unsigned long flags;
427 unsigned long pulse_end;
428
429 /* avoid interference with interrupt */
430 spin_lock_irqsave(&timer_lock, flags);
431 if (last_value) {
432 /* clear unread bits in UART and restart */
433 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
434 /* determine 'virtual' pulse end: */
435 pulse_end = delta(&last_tv, &last_intr_tv);
436 dev_dbg(driver.dev, "timeout add %d for %lu usec\n",
437 last_value, pulse_end);
438 add_read_queue(last_value, pulse_end);
439 last_value = 0;
440 last_tv = last_intr_tv;
441 }
442 spin_unlock_irqrestore(&timer_lock, flags);
443 }
444
sir_interrupt(int irq,void * dev_id)445 static irqreturn_t sir_interrupt(int irq, void *dev_id)
446 {
447 unsigned char data;
448 struct timeval curr_tv;
449 static unsigned long deltv;
450 unsigned long deltintrtv;
451 unsigned long flags;
452 int iir, lsr;
453
454 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
455 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
456 case UART_IIR_MSI:
457 (void) inb(io + UART_MSR);
458 break;
459 case UART_IIR_RLSI:
460 (void) inb(io + UART_LSR);
461 break;
462 case UART_IIR_THRI:
463 #if 0
464 if (lsr & UART_LSR_THRE) /* FIFO is empty */
465 outb(data, io + UART_TX)
466 #endif
467 break;
468 case UART_IIR_RDI:
469 /* avoid interference with timer */
470 spin_lock_irqsave(&timer_lock, flags);
471 do {
472 del_timer(&timerlist);
473 data = inb(io + UART_RX);
474 do_gettimeofday(&curr_tv);
475 deltv = delta(&last_tv, &curr_tv);
476 deltintrtv = delta(&last_intr_tv, &curr_tv);
477 dev_dbg(driver.dev, "t %lu, d %d\n",
478 deltintrtv, (int)data);
479 /*
480 * if nothing came in last X cycles,
481 * it was gap
482 */
483 if (deltintrtv > TIME_CONST * threshold) {
484 if (last_value) {
485 dev_dbg(driver.dev, "GAP\n");
486 /* simulate signal change */
487 add_read_queue(last_value,
488 deltv -
489 deltintrtv);
490 last_value = 0;
491 last_tv.tv_sec =
492 last_intr_tv.tv_sec;
493 last_tv.tv_usec =
494 last_intr_tv.tv_usec;
495 deltv = deltintrtv;
496 }
497 }
498 data = 1;
499 if (data ^ last_value) {
500 /*
501 * deltintrtv > 2*TIME_CONST, remember?
502 * the other case is timeout
503 */
504 add_read_queue(last_value,
505 deltv-TIME_CONST);
506 last_value = data;
507 last_tv = curr_tv;
508 if (last_tv.tv_usec >= TIME_CONST) {
509 last_tv.tv_usec -= TIME_CONST;
510 } else {
511 last_tv.tv_sec--;
512 last_tv.tv_usec += 1000000 -
513 TIME_CONST;
514 }
515 }
516 last_intr_tv = curr_tv;
517 if (data) {
518 /*
519 * start timer for end of
520 * sequence detection
521 */
522 timerlist.expires = jiffies +
523 SIR_TIMEOUT;
524 add_timer(&timerlist);
525 }
526
527 lsr = inb(io + UART_LSR);
528 } while (lsr & UART_LSR_DR); /* data ready */
529 spin_unlock_irqrestore(&timer_lock, flags);
530 break;
531 default:
532 break;
533 }
534 }
535 return IRQ_RETVAL(IRQ_HANDLED);
536 }
537
send_space(unsigned long len)538 static void send_space(unsigned long len)
539 {
540 safe_udelay(len);
541 }
542
send_pulse(unsigned long len)543 static void send_pulse(unsigned long len)
544 {
545 long bytes_out = len / TIME_CONST;
546
547 if (bytes_out == 0)
548 bytes_out++;
549
550 while (bytes_out--) {
551 outb(PULSE, io + UART_TX);
552 /* FIXME treba seriozne cakanie z char/serial.c */
553 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
554 ;
555 }
556 }
557
init_hardware(void)558 static int init_hardware(void)
559 {
560 unsigned long flags;
561
562 spin_lock_irqsave(&hardware_lock, flags);
563 /* reset UART */
564 #if defined(LIRC_SIR_TEKRAM)
565 /* disable FIFO */
566 soutp(UART_FCR,
567 UART_FCR_CLEAR_RCVR|
568 UART_FCR_CLEAR_XMIT|
569 UART_FCR_TRIGGER_1);
570
571 /* Set DLAB 0. */
572 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
573
574 /* First of all, disable all interrupts */
575 soutp(UART_IER, sinp(UART_IER) &
576 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
577
578 /* Set DLAB 1. */
579 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
580
581 /* Set divisor to 12 => 9600 Baud */
582 soutp(UART_DLM, 0);
583 soutp(UART_DLL, 12);
584
585 /* Set DLAB 0. */
586 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
587
588 /* power supply */
589 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
590 safe_udelay(50*1000);
591
592 /* -DTR low -> reset PIC */
593 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
594 udelay(1*1000);
595
596 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
597 udelay(100);
598
599
600 /* -RTS low -> send control byte */
601 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
602 udelay(7);
603 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
604
605 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
606 udelay(1500);
607
608 /* back to normal operation */
609 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
610 udelay(50);
611
612 udelay(1500);
613
614 /* read previous control byte */
615 pr_info("0x%02x\n", sinp(UART_RX));
616
617 /* Set DLAB 1. */
618 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
619
620 /* Set divisor to 1 => 115200 Baud */
621 soutp(UART_DLM, 0);
622 soutp(UART_DLL, 1);
623
624 /* Set DLAB 0, 8 Bit */
625 soutp(UART_LCR, UART_LCR_WLEN8);
626 /* enable interrupts */
627 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
628 #else
629 outb(0, io + UART_MCR);
630 outb(0, io + UART_IER);
631 /* init UART */
632 /* set DLAB, speed = 115200 */
633 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
634 outb(1, io + UART_DLL); outb(0, io + UART_DLM);
635 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
636 outb(UART_LCR_WLEN7, io + UART_LCR);
637 /* FIFO operation */
638 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
639 /* interrupts */
640 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
641 outb(UART_IER_RDI, io + UART_IER);
642 /* turn on UART */
643 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
644 #ifdef LIRC_SIR_ACTISYS_ACT200L
645 init_act200();
646 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
647 init_act220();
648 #endif
649 #endif
650 spin_unlock_irqrestore(&hardware_lock, flags);
651 return 0;
652 }
653
drop_hardware(void)654 static void drop_hardware(void)
655 {
656 unsigned long flags;
657
658 spin_lock_irqsave(&hardware_lock, flags);
659
660 /* turn off interrupts */
661 outb(0, io + UART_IER);
662
663 spin_unlock_irqrestore(&hardware_lock, flags);
664 }
665
666 /* SECTION: Initialisation */
667
init_port(void)668 static int init_port(void)
669 {
670 int retval;
671
672 /* get I/O port access and IRQ line */
673 if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
674 pr_err("i/o port 0x%.4x already in use.\n", io);
675 return -EBUSY;
676 }
677 retval = request_irq(irq, sir_interrupt, 0,
678 LIRC_DRIVER_NAME, NULL);
679 if (retval < 0) {
680 release_region(io, 8);
681 pr_err("IRQ %d already in use.\n", irq);
682 return retval;
683 }
684 pr_info("I/O port 0x%.4x, IRQ %d.\n", io, irq);
685
686 setup_timer(&timerlist, sir_timeout, 0);
687
688 return 0;
689 }
690
drop_port(void)691 static void drop_port(void)
692 {
693 free_irq(irq, NULL);
694 del_timer_sync(&timerlist);
695 release_region(io, 8);
696 }
697
698 #ifdef LIRC_SIR_ACTISYS_ACT200L
699 /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
700 /* some code borrowed from Linux IRDA driver */
701
702 /* Register 0: Control register #1 */
703 #define ACT200L_REG0 0x00
704 #define ACT200L_TXEN 0x01 /* Enable transmitter */
705 #define ACT200L_RXEN 0x02 /* Enable receiver */
706 #define ACT200L_ECHO 0x08 /* Echo control chars */
707
708 /* Register 1: Control register #2 */
709 #define ACT200L_REG1 0x10
710 #define ACT200L_LODB 0x01 /* Load new baud rate count value */
711 #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */
712
713 /* Register 3: Transmit mode register #2 */
714 #define ACT200L_REG3 0x30
715 #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
716 #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
717 #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */
718
719 /* Register 4: Output Power register */
720 #define ACT200L_REG4 0x40
721 #define ACT200L_OP0 0x01 /* Enable LED1C output */
722 #define ACT200L_OP1 0x02 /* Enable LED2C output */
723 #define ACT200L_BLKR 0x04
724
725 /* Register 5: Receive Mode register */
726 #define ACT200L_REG5 0x50
727 #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */
728 /*.. other various IRDA bit modes, and TV remote modes..*/
729
730 /* Register 6: Receive Sensitivity register #1 */
731 #define ACT200L_REG6 0x60
732 #define ACT200L_RS0 0x01 /* receive threshold bit 0 */
733 #define ACT200L_RS1 0x02 /* receive threshold bit 1 */
734
735 /* Register 7: Receive Sensitivity register #2 */
736 #define ACT200L_REG7 0x70
737 #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */
738
739 /* Register 8,9: Baud Rate Divider register #1,#2 */
740 #define ACT200L_REG8 0x80
741 #define ACT200L_REG9 0x90
742
743 #define ACT200L_2400 0x5f
744 #define ACT200L_9600 0x17
745 #define ACT200L_19200 0x0b
746 #define ACT200L_38400 0x05
747 #define ACT200L_57600 0x03
748 #define ACT200L_115200 0x01
749
750 /* Register 13: Control register #3 */
751 #define ACT200L_REG13 0xd0
752 #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */
753
754 /* Register 15: Status register */
755 #define ACT200L_REG15 0xf0
756
757 /* Register 21: Control register #4 */
758 #define ACT200L_REG21 0x50
759 #define ACT200L_EXCK 0x02 /* Disable clock output driver */
760 #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */
761
init_act200(void)762 static void init_act200(void)
763 {
764 int i;
765 __u8 control[] = {
766 ACT200L_REG15,
767 ACT200L_REG13 | ACT200L_SHDW,
768 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
769 ACT200L_REG13,
770 ACT200L_REG7 | ACT200L_ENPOS,
771 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1,
772 ACT200L_REG5 | ACT200L_RWIDL,
773 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR,
774 ACT200L_REG3 | ACT200L_B0,
775 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN,
776 ACT200L_REG8 | (ACT200L_115200 & 0x0f),
777 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
778 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
779 };
780
781 /* Set DLAB 1. */
782 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
783
784 /* Set divisor to 12 => 9600 Baud */
785 soutp(UART_DLM, 0);
786 soutp(UART_DLL, 12);
787
788 /* Set DLAB 0. */
789 soutp(UART_LCR, UART_LCR_WLEN8);
790 /* Set divisor to 12 => 9600 Baud */
791
792 /* power supply */
793 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
794 for (i = 0; i < 50; i++)
795 safe_udelay(1000);
796
797 /* Reset the dongle : set RTS low for 25 ms */
798 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
799 for (i = 0; i < 25; i++)
800 udelay(1000);
801
802 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
803 udelay(100);
804
805 /* Clear DTR and set RTS to enter command mode */
806 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
807 udelay(7);
808
809 /* send out the control register settings for 115K 7N1 SIR operation */
810 for (i = 0; i < sizeof(control); i++) {
811 soutp(UART_TX, control[i]);
812 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
813 udelay(1500);
814 }
815
816 /* back to normal operation */
817 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
818 udelay(50);
819
820 udelay(1500);
821 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
822
823 /* Set DLAB 1. */
824 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
825
826 /* Set divisor to 1 => 115200 Baud */
827 soutp(UART_DLM, 0);
828 soutp(UART_DLL, 1);
829
830 /* Set DLAB 0. */
831 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
832
833 /* Set DLAB 0, 7 Bit */
834 soutp(UART_LCR, UART_LCR_WLEN7);
835
836 /* enable interrupts */
837 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
838 }
839 #endif
840
841 #ifdef LIRC_SIR_ACTISYS_ACT220L
842 /*
843 * Derived from linux IrDA driver (net/irda/actisys.c)
844 * Drop me a mail for any kind of comment: maxx@spaceboyz.net
845 */
846
init_act220(void)847 void init_act220(void)
848 {
849 int i;
850
851 /* DLAB 1 */
852 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
853
854 /* 9600 baud */
855 soutp(UART_DLM, 0);
856 soutp(UART_DLL, 12);
857
858 /* DLAB 0 */
859 soutp(UART_LCR, UART_LCR_WLEN7);
860
861 /* reset the dongle, set DTR low for 10us */
862 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
863 udelay(10);
864
865 /* back to normal (still 9600) */
866 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
867
868 /*
869 * send RTS pulses until we reach 115200
870 * i hope this is really the same for act220l/act220l+
871 */
872 for (i = 0; i < 3; i++) {
873 udelay(10);
874 /* set RTS low for 10 us */
875 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
876 udelay(10);
877 /* set RTS high for 10 us */
878 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
879 }
880
881 /* back to normal operation */
882 udelay(1500); /* better safe than sorry ;) */
883
884 /* Set DLAB 1. */
885 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
886
887 /* Set divisor to 1 => 115200 Baud */
888 soutp(UART_DLM, 0);
889 soutp(UART_DLL, 1);
890
891 /* Set DLAB 0, 7 Bit */
892 /* The dongle doesn't seem to have any problems with operation at 7N1 */
893 soutp(UART_LCR, UART_LCR_WLEN7);
894
895 /* enable interrupts */
896 soutp(UART_IER, UART_IER_RDI);
897 }
898 #endif
899
init_lirc_sir(void)900 static int init_lirc_sir(void)
901 {
902 int retval;
903
904 init_waitqueue_head(&lirc_read_queue);
905 retval = init_port();
906 if (retval < 0)
907 return retval;
908 init_hardware();
909 pr_info("Installed.\n");
910 return 0;
911 }
912
lirc_sir_probe(struct platform_device * dev)913 static int lirc_sir_probe(struct platform_device *dev)
914 {
915 return 0;
916 }
917
lirc_sir_remove(struct platform_device * dev)918 static int lirc_sir_remove(struct platform_device *dev)
919 {
920 return 0;
921 }
922
923 static struct platform_driver lirc_sir_driver = {
924 .probe = lirc_sir_probe,
925 .remove = lirc_sir_remove,
926 .driver = {
927 .name = "lirc_sir",
928 },
929 };
930
lirc_sir_init(void)931 static int __init lirc_sir_init(void)
932 {
933 int retval;
934
935 retval = platform_driver_register(&lirc_sir_driver);
936 if (retval) {
937 pr_err("Platform driver register failed!\n");
938 return -ENODEV;
939 }
940
941 lirc_sir_dev = platform_device_alloc("lirc_dev", 0);
942 if (!lirc_sir_dev) {
943 pr_err("Platform device alloc failed!\n");
944 retval = -ENOMEM;
945 goto pdev_alloc_fail;
946 }
947
948 retval = platform_device_add(lirc_sir_dev);
949 if (retval) {
950 pr_err("Platform device add failed!\n");
951 retval = -ENODEV;
952 goto pdev_add_fail;
953 }
954
955 retval = init_chrdev();
956 if (retval < 0)
957 goto fail;
958
959 retval = init_lirc_sir();
960 if (retval) {
961 drop_chrdev();
962 goto fail;
963 }
964
965 return 0;
966
967 fail:
968 platform_device_del(lirc_sir_dev);
969 pdev_add_fail:
970 platform_device_put(lirc_sir_dev);
971 pdev_alloc_fail:
972 platform_driver_unregister(&lirc_sir_driver);
973 return retval;
974 }
975
lirc_sir_exit(void)976 static void __exit lirc_sir_exit(void)
977 {
978 drop_hardware();
979 drop_chrdev();
980 drop_port();
981 platform_device_unregister(lirc_sir_dev);
982 platform_driver_unregister(&lirc_sir_driver);
983 pr_info("Uninstalled.\n");
984 }
985
986 module_init(lirc_sir_init);
987 module_exit(lirc_sir_exit);
988
989 #ifdef LIRC_SIR_TEKRAM
990 MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
991 MODULE_AUTHOR("Christoph Bartelmus");
992 #elif defined(LIRC_SIR_ACTISYS_ACT200L)
993 MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
994 MODULE_AUTHOR("Karl Bongers");
995 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
996 MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
997 MODULE_AUTHOR("Jan Roemisch");
998 #else
999 MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
1000 MODULE_AUTHOR("Milan Pikula");
1001 #endif
1002 MODULE_LICENSE("GPL");
1003
1004 module_param(io, int, S_IRUGO);
1005 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1006
1007 module_param(irq, int, S_IRUGO);
1008 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1009
1010 module_param(threshold, int, S_IRUGO);
1011 MODULE_PARM_DESC(threshold, "space detection threshold (3)");
1012
1013 module_param(debug, bool, S_IRUGO | S_IWUSR);
1014 MODULE_PARM_DESC(debug, "Enable debugging messages");
1015