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Searched refs:DMA_RB_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Dni_dma.c166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
171 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
173 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
215 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
246 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); in cayman_dma_resume()
Dr600_dma.c101 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop()
107 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
136 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
Dni.c1831 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1833 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1838 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1840 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
Dsi.c3878 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3880 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3884 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3886 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4045 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4047 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4049 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4051 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
Dnid.h1296 #define DMA_RB_CNTL 0xd000 macro
Dr600.c1654 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset()
1656 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset()
1785 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset()
1787 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
Dsid.h1813 #define DMA_RB_CNTL 0xd000 macro
Devergreen.c3953 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
3955 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
4062 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4064 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
Devergreend.h2573 #define DMA_RB_CNTL 0xd000 macro
Dr600d.h613 #define DMA_RB_CNTL 0xd000 macro