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Searched refs:DPLL_FPA01_P1_POST_DIV_SHIFT (Results 1 – 5 of 5) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/gma500/
Dpsb_intel_display.c349 DPLL_FPA01_P1_POST_DIV_SHIFT); in psb_intel_crtc_clock_get()
365 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in psb_intel_crtc_clock_get()
Dcdv_intel_display.c889 DPLL_FPA01_P1_POST_DIV_SHIFT); in cdv_intel_crtc_clock_get()
909 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in cdv_intel_crtc_clock_get()
Dpsb_intel_reg.h266 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_display.c6511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_update_pll()
6565 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_update_pll()
6570 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_update_pll()
7810 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
9251 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()
9278 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()
9289 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in i9xx_crtc_clock_get()
Di915_reg.h1891 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro