Home
last modified time | relevance | path

Searched refs:EVERGREEN_CRTC2_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Devergreen_reg.h226 #define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) macro
Devergreen.c42 EVERGREEN_CRTC2_REGISTER_OFFSET,
4513 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4524 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4590 …afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4733 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in evergreen_irq_set()
4746 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_irq_set()
4771 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); in evergreen_irq_set()
4795 …ev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4805 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4825 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
[all …]
Dradeon_display.c1499 EVERGREEN_CRTC2_REGISTER_OFFSET, in radeon_afmt_init()
1823 EVERGREEN_CRTC2_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1825 EVERGREEN_CRTC2_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dsi.c5952 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5965 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6198 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in si_irq_set()
6213 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in si_irq_set()
6258 …ev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in si_irq_ack()
6281 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6285 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6287 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
Dradeon_dp_mst.c16 EVERGREEN_CRTC2_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c7308 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7321 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7591 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in cik_irq_set()
7606 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set()
7658 EVERGREEN_CRTC2_REGISTER_OFFSET); in cik_irq_ack()
7686 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_ack()
7692 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7694 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c660 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | in radeon_card_posted()
Devergreen_cs.c1027 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1035 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2222 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()