| /linux-4.4.14/include/dt-bindings/clock/ |
| D | exynos4.h | 242 #define CLK_PPMURIGHT 401 macro
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| D | exynos3250.h | 140 #define CLK_PPMURIGHT 136 macro
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| D | exynos4415.h | 193 #define CLK_PPMURIGHT 198 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 242 #define CLK_PPMURIGHT 401 macro
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| D | exynos3250.h | 140 #define CLK_PPMURIGHT 136 macro
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| D | exynos4415.h | 193 #define CLK_PPMURIGHT 198 macro
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 242 #define CLK_PPMURIGHT 401 macro
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| D | exynos3250.h | 140 #define CLK_PPMURIGHT 136 macro
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| D | exynos4415.h | 193 #define CLK_PPMURIGHT 198 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 242 #define CLK_PPMURIGHT 401 macro
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| D | exynos3250.h | 140 #define CLK_PPMURIGHT 136 macro
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| D | exynos4415.h | 193 #define CLK_PPMURIGHT 198 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 242 #define CLK_PPMURIGHT 401 macro
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| D | exynos3250.h | 140 #define CLK_PPMURIGHT 136 macro
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| D | exynos4415.h | 193 #define CLK_PPMURIGHT 198 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 242 #define CLK_PPMURIGHT 401 macro
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| D | exynos3250.h | 140 #define CLK_PPMURIGHT 136 macro
|
| D | exynos4415.h | 193 #define CLK_PPMURIGHT 198 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 242 #define CLK_PPMURIGHT 401 macro
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| D | exynos3250.h | 140 #define CLK_PPMURIGHT 136 macro
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| D | exynos4415.h | 193 #define CLK_PPMURIGHT 198 macro
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| /linux-4.4.14/Documentation/devicetree/bindings/devfreq/event/ |
| D | exynos-ppmu.txt | 44 clocks = <&cmu CLK_PPMURIGHT>;
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | exynos3250.dtsi | 638 clocks = <&cmu CLK_PPMURIGHT>;
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| D | exynos4.dtsi | 773 clocks = <&clock CLK_PPMURIGHT>;
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-exynos4415.c | 617 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
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| D | clk-exynos3250.c | 452 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
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| D | clk-exynos4.c | 847 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
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