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Searched refs:EVERGREEN_CRTC3_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Devergreen_reg.h227 #define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) macro
Devergreen.c112 EVERGREEN_CRTC3_REGISTER_OFFSET,
4562 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4573 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4639 …afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4782 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in evergreen_irq_set()
4796 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_irq_set()
4820 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); in evergreen_irq_set()
4844 …ev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4854 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4875 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
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Dradeon_display.c1553 EVERGREEN_CRTC3_REGISTER_OFFSET, in radeon_afmt_init()
1894 EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1896 EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dsi.c5956 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5969 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6202 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in si_irq_set()
6218 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in si_irq_set()
6262 …ev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); in si_irq_ack()
6286 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6292 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6294 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
Dradeon_dp_mst.c17 EVERGREEN_CRTC3_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c7330 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7343 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7613 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in cik_irq_set()
7629 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set()
7681 EVERGREEN_CRTC3_REGISTER_OFFSET); in cik_irq_ack()
7710 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_ack()
7717 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7719 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c661 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_card_posted()
Devergreen_cs.c1031 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1039 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2235 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()