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Searched refs:EVERGREEN_CRTC5_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Devergreen_reg.h229 #define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) macro
Devergreen.c114 EVERGREEN_CRTC5_REGISTER_OFFSET
4566 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4577 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4641 …afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4786 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in evergreen_irq_set()
4802 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in evergreen_irq_set()
4822 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); in evergreen_irq_set()
4848 …ev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4856 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4890 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
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Dradeon_display.c1555 EVERGREEN_CRTC5_REGISTER_OFFSET, in radeon_afmt_init()
1908 EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1910 EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dsi.c5960 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5973 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6206 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in si_irq_set()
6224 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in si_irq_set()
6266 …ev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in si_irq_ack()
6301 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6307 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6309 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
Dradeon_dp_mst.c19 EVERGREEN_CRTC5_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c7334 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7347 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7617 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in cik_irq_set()
7635 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_set()
7687 EVERGREEN_CRTC5_REGISTER_OFFSET); in cik_irq_ack()
7727 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_ack()
7734 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7736 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c665 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_card_posted()
Devergreen_cs.c1033 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET in evergreen_cs_packet_parse_vline()
1041 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2241 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()