Searched refs:IMX7D_PLL_ENET_MAIN_100M_CLK (Results 1 – 9 of 9) sorted by relevance
109 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;135 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
56 #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 macro
464 …clks[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe… in imx7d_clocks_init()865 clk_set_parent(clks[IMX7D_ENET1_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); in imx7d_clocks_init()866 clk_set_parent(clks[IMX7D_ENET2_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); in imx7d_clocks_init()