Searched refs:PRCMU_DSI0ESCCLK (Results 1 – 11 of 11) sorted by relevance
69 #define PRCMU_DSI0ESCCLK 49 macro
243 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); in u8500_clk_init()244 prcmu_clk[PRCMU_DSI0ESCCLK] = clk; in u8500_clk_init()
232 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); in u8540_clk_init()
1480 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) in db8500_prcmu_request_clock()1481 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); in db8500_prcmu_request_clock()1654 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) in prcmu_clock_rate()1655 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); in prcmu_clock_rate()1822 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) in prcmu_round_clock_rate()1982 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) in prcmu_set_clock_rate()1983 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); in prcmu_set_clock_rate()
1218 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */