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Searched refs:TEGRA20_CLK_PLL_A_OUT0 (Results 1 – 18 of 18) sorted by relevance

/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dtegra20-car.h135 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dtegra20-car.h135 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dtegra20-car.h135 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dtegra20-car.h135 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dtegra20-car.h135 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux-4.4.14/include/dt-bindings/clock/
Dtegra20-car.h135 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dtegra20-car.h135 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux-4.4.14/drivers/clk/tegra/
Dclk-tegra20.c444 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
700 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
1047 {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1},
1050 {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1051 {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
/linux-4.4.14/arch/arm/boot/dts/
Dtegra20-plutux.dts57 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-tec.dts66 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-medcom-wide.dts85 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-trimslice.dts464 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-colibri-512.dtsi529 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-paz00.dts594 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-whistler.dts628 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-ventana.dts698 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-harmony.dts773 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
Dtegra20-seaboard.dts932 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,