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Searched refs:uart_parents (Results 1 – 4 of 4) sorted by relevance

/linux-4.4.14/drivers/clk/spear/
Dspear1310_clock.c378 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; variable
952 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, in spear1310_clk_init()
953 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
963 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, in spear1310_clk_init()
964 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
974 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, in spear1310_clk_init()
975 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
985 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, in spear1310_clk_init()
986 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
996 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, in spear1310_clk_init()
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Dspear6xx_clock.c101 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", }; variable
170 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, in spear6xx_clk_init()
171 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, in spear6xx_clk_init()
/linux-4.4.14/drivers/clk/mediatek/
Dclk-mt8135.c233 static const char * const uart_parents[] __initconst = { variable
381 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
Dclk-mt8173.c233 static const char * const uart_parents[] __initconst = { variable
542 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),