1 #ifndef __LINUX_FOTG210_H
2 #define __LINUX_FOTG210_H
3
4 #include <linux/usb/ehci-dbgp.h>
5
6 /* definitions used for the EHCI driver */
7
8 /*
9 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
10 * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
11 * the host controller implementation.
12 *
13 * To facilitate the strongest possible byte-order checking from "sparse"
14 * and so on, we use __leXX unless that's not practical.
15 */
16 #define __hc32 __le32
17 #define __hc16 __le16
18
19 /* statistics can be kept for tuning/monitoring */
20 struct fotg210_stats {
21 /* irq usage */
22 unsigned long normal;
23 unsigned long error;
24 unsigned long iaa;
25 unsigned long lost_iaa;
26
27 /* termination of urbs from core */
28 unsigned long complete;
29 unsigned long unlink;
30 };
31
32 /* fotg210_hcd->lock guards shared data against other CPUs:
33 * fotg210_hcd: async, unlink, periodic (and shadow), ...
34 * usb_host_endpoint: hcpriv
35 * fotg210_qh: qh_next, qtd_list
36 * fotg210_qtd: qtd_list
37 *
38 * Also, hold this lock when talking to HC registers or
39 * when updating hw_* fields in shared qh/qtd/... structures.
40 */
41
42 #define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
43
44 /*
45 * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
46 * controller may be doing DMA. Lower values mean there's no DMA.
47 */
48 enum fotg210_rh_state {
49 FOTG210_RH_HALTED,
50 FOTG210_RH_SUSPENDED,
51 FOTG210_RH_RUNNING,
52 FOTG210_RH_STOPPING
53 };
54
55 /*
56 * Timer events, ordered by increasing delay length.
57 * Always update event_delays_ns[] and event_handlers[] (defined in
58 * ehci-timer.c) in parallel with this list.
59 */
60 enum fotg210_hrtimer_event {
61 FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */
62 FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
63 FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
64 FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
65 FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
66 FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
67 FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
68 FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
69 FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
70 FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
71 FOTG210_HRTIMER_NUM_EVENTS /* Must come last */
72 };
73 #define FOTG210_HRTIMER_NO_EVENT 99
74
75 struct fotg210_hcd { /* one per controller */
76 /* timing support */
77 enum fotg210_hrtimer_event next_hrtimer_event;
78 unsigned enabled_hrtimer_events;
79 ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
80 struct hrtimer hrtimer;
81
82 int PSS_poll_count;
83 int ASS_poll_count;
84 int died_poll_count;
85
86 /* glue to PCI and HCD framework */
87 struct fotg210_caps __iomem *caps;
88 struct fotg210_regs __iomem *regs;
89 struct ehci_dbg_port __iomem *debug;
90
91 __u32 hcs_params; /* cached register copy */
92 spinlock_t lock;
93 enum fotg210_rh_state rh_state;
94
95 /* general schedule support */
96 bool scanning:1;
97 bool need_rescan:1;
98 bool intr_unlinking:1;
99 bool async_unlinking:1;
100 bool shutdown:1;
101 struct fotg210_qh *qh_scan_next;
102
103 /* async schedule support */
104 struct fotg210_qh *async;
105 struct fotg210_qh *dummy; /* For AMD quirk use */
106 struct fotg210_qh *async_unlink;
107 struct fotg210_qh *async_unlink_last;
108 struct fotg210_qh *async_iaa;
109 unsigned async_unlink_cycle;
110 unsigned async_count; /* async activity count */
111
112 /* periodic schedule support */
113 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
114 unsigned periodic_size;
115 __hc32 *periodic; /* hw periodic table */
116 dma_addr_t periodic_dma;
117 struct list_head intr_qh_list;
118 unsigned i_thresh; /* uframes HC might cache */
119
120 union fotg210_shadow *pshadow; /* mirror hw periodic table */
121 struct fotg210_qh *intr_unlink;
122 struct fotg210_qh *intr_unlink_last;
123 unsigned intr_unlink_cycle;
124 unsigned now_frame; /* frame from HC hardware */
125 unsigned next_frame; /* scan periodic, start here */
126 unsigned intr_count; /* intr activity count */
127 unsigned isoc_count; /* isoc activity count */
128 unsigned periodic_count; /* periodic activity count */
129 /* max periodic time per uframe */
130 unsigned uframe_periodic_max;
131
132
133 /* list of itds completed while now_frame was still active */
134 struct list_head cached_itd_list;
135 struct fotg210_itd *last_itd_to_free;
136
137 /* per root hub port */
138 unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
139
140 /* bit vectors (one bit per port) */
141 unsigned long bus_suspended; /* which ports were
142 already suspended at the start of a bus suspend */
143 unsigned long companion_ports; /* which ports are
144 dedicated to the companion controller */
145 unsigned long owned_ports; /* which ports are
146 owned by the companion during a bus suspend */
147 unsigned long port_c_suspend; /* which ports have
148 the change-suspend feature turned on */
149 unsigned long suspended_ports; /* which ports are
150 suspended */
151 unsigned long resuming_ports; /* which ports have
152 started to resume */
153
154 /* per-HC memory pools (could be per-bus, but ...) */
155 struct dma_pool *qh_pool; /* qh per active urb */
156 struct dma_pool *qtd_pool; /* one or more per qh */
157 struct dma_pool *itd_pool; /* itd per iso urb */
158
159 unsigned random_frame;
160 unsigned long next_statechange;
161 ktime_t last_periodic_enable;
162 u32 command;
163
164 /* SILICON QUIRKS */
165 unsigned need_io_watchdog:1;
166 unsigned fs_i_thresh:1; /* Intel iso scheduling */
167
168 u8 sbrn; /* packed release number */
169
170 /* irq statistics */
171 #ifdef FOTG210_STATS
172 struct fotg210_stats stats;
173 # define COUNT(x) ((x)++)
174 #else
175 # define COUNT(x)
176 #endif
177
178 /* debug files */
179 struct dentry *debug_dir;
180 };
181
182 /* convert between an HCD pointer and the corresponding FOTG210_HCD */
hcd_to_fotg210(struct usb_hcd * hcd)183 static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
184 {
185 return (struct fotg210_hcd *)(hcd->hcd_priv);
186 }
fotg210_to_hcd(struct fotg210_hcd * fotg210)187 static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
188 {
189 return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
190 }
191
192 /*-------------------------------------------------------------------------*/
193
194 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
195
196 /* Section 2.2 Host Controller Capability Registers */
197 struct fotg210_caps {
198 /* these fields are specified as 8 and 16 bit registers,
199 * but some hosts can't perform 8 or 16 bit PCI accesses.
200 * some hosts treat caplength and hciversion as parts of a 32-bit
201 * register, others treat them as two separate registers, this
202 * affects the memory map for big endian controllers.
203 */
204 u32 hc_capbase;
205 #define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
206 (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
207 #define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
208 (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
209 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
210 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
211
212 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
213 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
214 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
215 u8 portroute[8]; /* nibbles for routing - offset 0xC */
216 };
217
218
219 /* Section 2.3 Host Controller Operational Registers */
220 struct fotg210_regs {
221
222 /* USBCMD: offset 0x00 */
223 u32 command;
224
225 /* EHCI 1.1 addendum */
226 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
227 #define CMD_PARK (1<<11) /* enable "park" on async qh */
228 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
229 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
230 #define CMD_ASE (1<<5) /* async schedule enable */
231 #define CMD_PSE (1<<4) /* periodic schedule enable */
232 /* 3:2 is periodic frame list size */
233 #define CMD_RESET (1<<1) /* reset HC not bus */
234 #define CMD_RUN (1<<0) /* start/stop HC */
235
236 /* USBSTS: offset 0x04 */
237 u32 status;
238 #define STS_ASS (1<<15) /* Async Schedule Status */
239 #define STS_PSS (1<<14) /* Periodic Schedule Status */
240 #define STS_RECL (1<<13) /* Reclamation */
241 #define STS_HALT (1<<12) /* Not running (any reason) */
242 /* some bits reserved */
243 /* these STS_* flags are also intr_enable bits (USBINTR) */
244 #define STS_IAA (1<<5) /* Interrupted on async advance */
245 #define STS_FATAL (1<<4) /* such as some PCI access errors */
246 #define STS_FLR (1<<3) /* frame list rolled over */
247 #define STS_PCD (1<<2) /* port change detect */
248 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
249 #define STS_INT (1<<0) /* "normal" completion (short, ...) */
250
251 /* USBINTR: offset 0x08 */
252 u32 intr_enable;
253
254 /* FRINDEX: offset 0x0C */
255 u32 frame_index; /* current microframe number */
256 /* CTRLDSSEGMENT: offset 0x10 */
257 u32 segment; /* address bits 63:32 if needed */
258 /* PERIODICLISTBASE: offset 0x14 */
259 u32 frame_list; /* points to periodic list */
260 /* ASYNCLISTADDR: offset 0x18 */
261 u32 async_next; /* address of next async queue head */
262
263 u32 reserved1;
264 /* PORTSC: offset 0x20 */
265 u32 port_status;
266 /* 31:23 reserved */
267 #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
268 #define PORT_RESET (1<<8) /* reset port */
269 #define PORT_SUSPEND (1<<7) /* suspend port */
270 #define PORT_RESUME (1<<6) /* resume it */
271 #define PORT_PEC (1<<3) /* port enable change */
272 #define PORT_PE (1<<2) /* port enable */
273 #define PORT_CSC (1<<1) /* connect status change */
274 #define PORT_CONNECT (1<<0) /* device connected */
275 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
276 u32 reserved2[19];
277
278 /* OTGCSR: offet 0x70 */
279 u32 otgcsr;
280 #define OTGCSR_HOST_SPD_TYP (3 << 22)
281 #define OTGCSR_A_BUS_DROP (1 << 5)
282 #define OTGCSR_A_BUS_REQ (1 << 4)
283
284 /* OTGISR: offset 0x74 */
285 u32 otgisr;
286 #define OTGISR_OVC (1 << 10)
287
288 u32 reserved3[15];
289
290 /* GMIR: offset 0xB4 */
291 u32 gmir;
292 #define GMIR_INT_POLARITY (1 << 3) /*Active High*/
293 #define GMIR_MHC_INT (1 << 2)
294 #define GMIR_MOTG_INT (1 << 1)
295 #define GMIR_MDEV_INT (1 << 0)
296 };
297
298 /*-------------------------------------------------------------------------*/
299
300 #define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
301
302 /*
303 * EHCI Specification 0.95 Section 3.5
304 * QTD: describe data transfer components (buffer, direction, ...)
305 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
306 *
307 * These are associated only with "QH" (Queue Head) structures,
308 * used with control, bulk, and interrupt transfers.
309 */
310 struct fotg210_qtd {
311 /* first part defined by EHCI spec */
312 __hc32 hw_next; /* see EHCI 3.5.1 */
313 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
314 __hc32 hw_token; /* see EHCI 3.5.3 */
315 #define QTD_TOGGLE (1 << 31) /* data toggle */
316 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
317 #define QTD_IOC (1 << 15) /* interrupt on complete */
318 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
319 #define QTD_PID(tok) (((tok)>>8) & 0x3)
320 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
321 #define QTD_STS_HALT (1 << 6) /* halted on error */
322 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
323 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
324 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
325 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
326 #define QTD_STS_STS (1 << 1) /* split transaction state */
327 #define QTD_STS_PING (1 << 0) /* issue PING? */
328
329 #define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
330 #define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT)
331 #define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS)
332
333 __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
334 __hc32 hw_buf_hi[5]; /* Appendix B */
335
336 /* the rest is HCD-private */
337 dma_addr_t qtd_dma; /* qtd address */
338 struct list_head qtd_list; /* sw qtd list */
339 struct urb *urb; /* qtd's urb */
340 size_t length; /* length of buffer */
341 } __aligned(32);
342
343 /* mask NakCnt+T in qh->hw_alt_next */
344 #define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f)
345
346 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
347
348 /*-------------------------------------------------------------------------*/
349
350 /* type tag from {qh,itd,fstn}->hw_next */
351 #define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1))
352
353 /*
354 * Now the following defines are not converted using the
355 * cpu_to_le32() macro anymore, since we have to support
356 * "dynamic" switching between be and le support, so that the driver
357 * can be used on one system with SoC EHCI controller using big-endian
358 * descriptors as well as a normal little-endian PCI EHCI controller.
359 */
360 /* values for that type tag */
361 #define Q_TYPE_ITD (0 << 1)
362 #define Q_TYPE_QH (1 << 1)
363 #define Q_TYPE_SITD (2 << 1)
364 #define Q_TYPE_FSTN (3 << 1)
365
366 /* next async queue entry, or pointer to interrupt/periodic QH */
367 #define QH_NEXT(fotg210, dma) \
368 (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
369
370 /* for periodic/async schedules and qtd lists, mark end of list */
371 #define FOTG210_LIST_END(fotg210) \
372 cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
373
374 /*
375 * Entries in periodic shadow table are pointers to one of four kinds
376 * of data structure. That's dictated by the hardware; a type tag is
377 * encoded in the low bits of the hardware's periodic schedule. Use
378 * Q_NEXT_TYPE to get the tag.
379 *
380 * For entries in the async schedule, the type tag always says "qh".
381 */
382 union fotg210_shadow {
383 struct fotg210_qh *qh; /* Q_TYPE_QH */
384 struct fotg210_itd *itd; /* Q_TYPE_ITD */
385 struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */
386 __hc32 *hw_next; /* (all types) */
387 void *ptr;
388 };
389
390 /*-------------------------------------------------------------------------*/
391
392 /*
393 * EHCI Specification 0.95 Section 3.6
394 * QH: describes control/bulk/interrupt endpoints
395 * See Fig 3-7 "Queue Head Structure Layout".
396 *
397 * These appear in both the async and (for interrupt) periodic schedules.
398 */
399
400 /* first part defined by EHCI spec */
401 struct fotg210_qh_hw {
402 __hc32 hw_next; /* see EHCI 3.6.1 */
403 __hc32 hw_info1; /* see EHCI 3.6.2 */
404 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
405 #define QH_HEAD (1 << 15) /* Head of async reclamation list */
406 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
407 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
408 #define QH_LOW_SPEED (1 << 12)
409 #define QH_FULL_SPEED (0 << 12)
410 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
411 __hc32 hw_info2; /* see EHCI 3.6.2 */
412 #define QH_SMASK 0x000000ff
413 #define QH_CMASK 0x0000ff00
414 #define QH_HUBADDR 0x007f0000
415 #define QH_HUBPORT 0x3f800000
416 #define QH_MULT 0xc0000000
417 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
418
419 /* qtd overlay (hardware parts of a struct fotg210_qtd) */
420 __hc32 hw_qtd_next;
421 __hc32 hw_alt_next;
422 __hc32 hw_token;
423 __hc32 hw_buf[5];
424 __hc32 hw_buf_hi[5];
425 } __aligned(32);
426
427 struct fotg210_qh {
428 struct fotg210_qh_hw *hw; /* Must come first */
429 /* the rest is HCD-private */
430 dma_addr_t qh_dma; /* address of qh */
431 union fotg210_shadow qh_next; /* ptr to qh; or periodic */
432 struct list_head qtd_list; /* sw qtd list */
433 struct list_head intr_node; /* list of intr QHs */
434 struct fotg210_qtd *dummy;
435 struct fotg210_qh *unlink_next; /* next on unlink list */
436
437 unsigned unlink_cycle;
438
439 u8 needs_rescan; /* Dequeue during giveback */
440 u8 qh_state;
441 #define QH_STATE_LINKED 1 /* HC sees this */
442 #define QH_STATE_UNLINK 2 /* HC may still see this */
443 #define QH_STATE_IDLE 3 /* HC doesn't see this */
444 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
445 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
446
447 u8 xacterrs; /* XactErr retry counter */
448 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
449
450 /* periodic schedule info */
451 u8 usecs; /* intr bandwidth */
452 u8 gap_uf; /* uframes split/csplit gap */
453 u8 c_usecs; /* ... split completion bw */
454 u16 tt_usecs; /* tt downstream bandwidth */
455 unsigned short period; /* polling interval */
456 unsigned short start; /* where polling starts */
457 #define NO_FRAME ((unsigned short)~0) /* pick new start */
458
459 struct usb_device *dev; /* access to TT */
460 unsigned is_out:1; /* bulk or intr OUT */
461 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
462 };
463
464 /*-------------------------------------------------------------------------*/
465
466 /* description of one iso transaction (up to 3 KB data if highspeed) */
467 struct fotg210_iso_packet {
468 /* These will be copied to iTD when scheduling */
469 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
470 __hc32 transaction; /* itd->hw_transaction[i] |= */
471 u8 cross; /* buf crosses pages */
472 /* for full speed OUT splits */
473 u32 buf1;
474 };
475
476 /* temporary schedule data for packets from iso urbs (both speeds)
477 * each packet is one logical usb transaction to the device (not TT),
478 * beginning at stream->next_uframe
479 */
480 struct fotg210_iso_sched {
481 struct list_head td_list;
482 unsigned span;
483 struct fotg210_iso_packet packet[0];
484 };
485
486 /*
487 * fotg210_iso_stream - groups all (s)itds for this endpoint.
488 * acts like a qh would, if EHCI had them for ISO.
489 */
490 struct fotg210_iso_stream {
491 /* first field matches fotg210_hq, but is NULL */
492 struct fotg210_qh_hw *hw;
493
494 u8 bEndpointAddress;
495 u8 highspeed;
496 struct list_head td_list; /* queued itds */
497 struct list_head free_list; /* list of unused itds */
498 struct usb_device *udev;
499 struct usb_host_endpoint *ep;
500
501 /* output of (re)scheduling */
502 int next_uframe;
503 __hc32 splits;
504
505 /* the rest is derived from the endpoint descriptor,
506 * trusting urb->interval == f(epdesc->bInterval) and
507 * including the extra info for hw_bufp[0..2]
508 */
509 u8 usecs, c_usecs;
510 u16 interval;
511 u16 tt_usecs;
512 u16 maxp;
513 u16 raw_mask;
514 unsigned bandwidth;
515
516 /* This is used to initialize iTD's hw_bufp fields */
517 __hc32 buf0;
518 __hc32 buf1;
519 __hc32 buf2;
520
521 /* this is used to initialize sITD's tt info */
522 __hc32 address;
523 };
524
525 /*-------------------------------------------------------------------------*/
526
527 /*
528 * EHCI Specification 0.95 Section 3.3
529 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
530 *
531 * Schedule records for high speed iso xfers
532 */
533 struct fotg210_itd {
534 /* first part defined by EHCI spec */
535 __hc32 hw_next; /* see EHCI 3.3.1 */
536 __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
537 #define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
538 #define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */
539 #define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */
540 #define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
541 #define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
542 #define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */
543
544 #define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
545
546 __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
547 __hc32 hw_bufp_hi[7]; /* Appendix B */
548
549 /* the rest is HCD-private */
550 dma_addr_t itd_dma; /* for this itd */
551 union fotg210_shadow itd_next; /* ptr to periodic q entry */
552
553 struct urb *urb;
554 struct fotg210_iso_stream *stream; /* endpoint's queue */
555 struct list_head itd_list; /* list of stream's itds */
556
557 /* any/all hw_transactions here may be used by that urb */
558 unsigned frame; /* where scheduled */
559 unsigned pg;
560 unsigned index[8]; /* in urb->iso_frame_desc */
561 } __aligned(32);
562
563 /*-------------------------------------------------------------------------*/
564
565 /*
566 * EHCI Specification 0.96 Section 3.7
567 * Periodic Frame Span Traversal Node (FSTN)
568 *
569 * Manages split interrupt transactions (using TT) that span frame boundaries
570 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
571 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
572 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
573 */
574 struct fotg210_fstn {
575 __hc32 hw_next; /* any periodic q entry */
576 __hc32 hw_prev; /* qh or FOTG210_LIST_END */
577
578 /* the rest is HCD-private */
579 dma_addr_t fstn_dma;
580 union fotg210_shadow fstn_next; /* ptr to periodic q entry */
581 } __aligned(32);
582
583 /*-------------------------------------------------------------------------*/
584
585 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
586
587 #define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
588 fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup);
589
590 #define fotg210_prepare_ports_for_controller_resume(fotg210) \
591 fotg210_adjust_port_wakeup_flags(fotg210, false, false);
592
593 /*-------------------------------------------------------------------------*/
594
595 /*
596 * Some EHCI controllers have a Transaction Translator built into the
597 * root hub. This is a non-standard feature. Each controller will need
598 * to add code to the following inline functions, and call them as
599 * needed (mostly in root hub code).
600 */
601
602 static inline unsigned int
fotg210_get_speed(struct fotg210_hcd * fotg210,unsigned int portsc)603 fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
604 {
605 return (readl(&fotg210->regs->otgcsr)
606 & OTGCSR_HOST_SPD_TYP) >> 22;
607 }
608
609 /* Returns the speed of a device attached to a port on the root hub. */
610 static inline unsigned int
fotg210_port_speed(struct fotg210_hcd * fotg210,unsigned int portsc)611 fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
612 {
613 switch (fotg210_get_speed(fotg210, portsc)) {
614 case 0:
615 return 0;
616 case 1:
617 return USB_PORT_STAT_LOW_SPEED;
618 case 2:
619 default:
620 return USB_PORT_STAT_HIGH_SPEED;
621 }
622 }
623
624 /*-------------------------------------------------------------------------*/
625
626 #define fotg210_has_fsl_portno_bug(e) (0)
627
628 /*
629 * While most USB host controllers implement their registers in
630 * little-endian format, a minority (celleb companion chip) implement
631 * them in big endian format.
632 *
633 * This attempts to support either format at compile time without a
634 * runtime penalty, or both formats with the additional overhead
635 * of checking a flag bit.
636 *
637 */
638
639 #define fotg210_big_endian_mmio(e) 0
640 #define fotg210_big_endian_capbase(e) 0
641
fotg210_readl(const struct fotg210_hcd * fotg210,__u32 __iomem * regs)642 static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
643 __u32 __iomem *regs)
644 {
645 return readl(regs);
646 }
647
fotg210_writel(const struct fotg210_hcd * fotg210,const unsigned int val,__u32 __iomem * regs)648 static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
649 const unsigned int val, __u32 __iomem *regs)
650 {
651 writel(val, regs);
652 }
653
654 /* cpu to fotg210 */
cpu_to_hc32(const struct fotg210_hcd * fotg210,const u32 x)655 static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
656 {
657 return cpu_to_le32(x);
658 }
659
660 /* fotg210 to cpu */
hc32_to_cpu(const struct fotg210_hcd * fotg210,const __hc32 x)661 static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
662 {
663 return le32_to_cpu(x);
664 }
665
hc32_to_cpup(const struct fotg210_hcd * fotg210,const __hc32 * x)666 static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
667 const __hc32 *x)
668 {
669 return le32_to_cpup(x);
670 }
671
672 /*-------------------------------------------------------------------------*/
673
fotg210_read_frame_index(struct fotg210_hcd * fotg210)674 static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
675 {
676 return fotg210_readl(fotg210, &fotg210->regs->frame_index);
677 }
678
679 #define fotg210_itdlen(urb, desc, t) ({ \
680 usb_pipein((urb)->pipe) ? \
681 (desc)->length - FOTG210_ITD_LENGTH(t) : \
682 FOTG210_ITD_LENGTH(t); \
683 })
684 /*-------------------------------------------------------------------------*/
685
686 #endif /* __LINUX_FOTG210_H */
687