1 /*
2 * U300 clock implementation
3 * Copyright (C) 2007-2012 ST-Ericsson AB
4 * License terms: GNU General Public License (GPL) version 2
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7 */
8 #include <linux/clkdev.h>
9 #include <linux/slab.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/clk-provider.h>
13 #include <linux/spinlock.h>
14 #include <linux/of.h>
15 #include <linux/platform_data/clk-u300.h>
16
17 /* APP side SYSCON registers */
18 /* CLK Control Register 16bit (R/W) */
19 #define U300_SYSCON_CCR (0x0000)
20 #define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
21 #define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
22 #define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
23 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
24 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
25 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
26 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
27 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
28 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
29 /* CLK Status Register 16bit (R/W) */
30 #define U300_SYSCON_CSR (0x0004)
31 #define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
32 #define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
33 /* Reset lines for SLOW devices 16bit (R/W) */
34 #define U300_SYSCON_RSR (0x0014)
35 #define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
36 #define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
37 #define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
38 #define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
39 #define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
40 #define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
41 #define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
42 #define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
43 #define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
44 #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
45 /* Reset lines for FAST devices 16bit (R/W) */
46 #define U300_SYSCON_RFR (0x0018)
47 #define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
48 #define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
49 #define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
50 #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
51 #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
52 #define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
53 #define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
54 #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
55 /* Reset lines for the rest of the peripherals 16bit (R/W) */
56 #define U300_SYSCON_RRR (0x001c)
57 #define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
58 #define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
59 #define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
60 #define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
61 #define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
62 #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
63 #define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
64 #define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
65 #define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
66 #define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
67 #define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
68 #define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
69 #define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
70 /* Clock enable for SLOW peripherals 16bit (R/W) */
71 #define U300_SYSCON_CESR (0x0020)
72 #define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
73 #define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
74 #define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
75 #define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
76 #define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
77 #define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
78 #define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
79 #define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
80 #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
81 /* Clock enable for FAST peripherals 16bit (R/W) */
82 #define U300_SYSCON_CEFR (0x0024)
83 #define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
84 #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
85 #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
86 #define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
87 #define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
88 #define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
89 #define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
90 #define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
91 #define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
92 #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
93 /* Clock enable for the rest of the peripherals 16bit (R/W) */
94 #define U300_SYSCON_CERR (0x0028)
95 #define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
96 #define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
97 #define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
98 #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
99 #define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
100 #define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
101 #define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
102 #define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
103 #define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
104 #define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
105 #define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
106 #define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
107 #define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
108 #define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
109 /* Single block clock enable 16bit (-/W) */
110 #define U300_SYSCON_SBCER (0x002c)
111 #define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
112 #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
113 #define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
114 #define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
115 #define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
116 #define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
117 #define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
118 #define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
119 #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
120 #define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
121 #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
122 #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
123 #define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
124 #define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
125 #define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
126 #define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
127 #define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
128 #define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
129 #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
130 #define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
131 #define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
132 #define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
133 #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
134 #define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
135 #define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
136 #define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
137 #define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
138 #define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
139 #define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
140 #define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
141 #define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
142 #define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
143 #define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
144 /* Single block clock disable 16bit (-/W) */
145 #define U300_SYSCON_SBCDR (0x0030)
146 /* Same values as above for SBCER */
147 /* Clock force SLOW peripherals 16bit (R/W) */
148 #define U300_SYSCON_CFSR (0x003c)
149 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
150 #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
151 #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
152 #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
153 #define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
154 #define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
155 #define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
156 #define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
157 #define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
158 /* Clock force FAST peripherals 16bit (R/W) */
159 #define U300_SYSCON_CFFR (0x40)
160 /* Values not defined. Define if you want to use them. */
161 /* Clock force the rest of the peripherals 16bit (R/W) */
162 #define U300_SYSCON_CFRR (0x44)
163 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
164 #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
165 #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
166 #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
167 #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
168 #define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
169 #define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
170 #define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
171 #define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
172 #define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
173 #define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
174 #define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
175 #define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
176 #define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
177 /* PLL208 Frequency Control 16bit (R/W) */
178 #define U300_SYSCON_PFCR (0x48)
179 #define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
180 /* Power Management Control 16bit (R/W) */
181 #define U300_SYSCON_PMCR (0x50)
182 #define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
183 #define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
184 /* Reset Out 16bit (R/W) */
185 #define U300_SYSCON_RCR (0x6c)
186 #define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
187 /* EMIF Slew Rate Control 16bit (R/W) */
188 #define U300_SYSCON_SRCLR (0x70)
189 #define U300_SYSCON_SRCLR_MASK (0x03FF)
190 #define U300_SYSCON_SRCLR_VALUE (0x03FF)
191 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
192 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
193 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
194 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
195 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
196 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
197 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
198 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
199 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
200 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
201 /* EMIF Clock Control Register 16bit (R/W) */
202 #define U300_SYSCON_ECCR (0x0078)
203 #define U300_SYSCON_ECCR_MASK (0x000F)
204 #define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
205 #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
206 #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
207 #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
208 /* MMC/MSPRO frequency divider register 0 16bit (R/W) */
209 #define U300_SYSCON_MMF0R (0x90)
210 #define U300_SYSCON_MMF0R_MASK (0x00FF)
211 #define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
212 #define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
213 /* MMC/MSPRO frequency divider register 1 16bit (R/W) */
214 #define U300_SYSCON_MMF1R (0x94)
215 #define U300_SYSCON_MMF1R_MASK (0x00FF)
216 #define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
217 #define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
218 /* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
219 #define U300_SYSCON_MMCR (0x9C)
220 #define U300_SYSCON_MMCR_MASK (0x0003)
221 #define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
222 #define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
223 /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
224 #define U300_SYSCON_S0CCR (0x120)
225 #define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
226 #define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
227 #define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
228 #define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
229 #define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
230 #define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
231 #define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
232 #define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
233 #define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
234 #define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
235 #define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
236 #define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
237 #define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
238 #define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
239 #define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
240 #define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
241 /* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
242 #define U300_SYSCON_S1CCR (0x124)
243 #define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
244 #define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
245 #define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
246 #define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
247 #define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
248 #define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
249 #define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
250 #define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
251 #define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
252 #define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
253 #define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
254 #define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
255 #define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
256 #define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
257 #define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
258 #define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
259 /* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
260 #define U300_SYSCON_S2CCR (0x128)
261 #define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
262 #define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
263 #define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
264 #define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
265 #define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
266 #define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
267 #define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
268 #define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
269 #define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
270 #define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
271 #define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
272 #define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
273 #define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
274 #define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
275 #define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
276 #define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
277 #define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
278 /* SC_PLL_IRQ_CONTROL 16bit (R/W) */
279 #define U300_SYSCON_PICR (0x0130)
280 #define U300_SYSCON_PICR_MASK (0x00FF)
281 #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
282 #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
283 #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
284 #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
285 #define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
286 #define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
287 #define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
288 #define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
289 /* SC_PLL_IRQ_STATUS 16 bit (R/-) */
290 #define U300_SYSCON_PISR (0x0134)
291 #define U300_SYSCON_PISR_MASK (0x000F)
292 #define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
293 #define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
294 #define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
295 #define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
296 /* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
297 #define U300_SYSCON_PICLR (0x0138)
298 #define U300_SYSCON_PICLR_MASK (0x000F)
299 #define U300_SYSCON_PICLR_RWMASK (0x0000)
300 #define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
301 #define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
302 #define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
303 #define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
304 /* Clock activity observability register 0 */
305 #define U300_SYSCON_C0OAR (0x140)
306 #define U300_SYSCON_C0OAR_MASK (0xFFFF)
307 #define U300_SYSCON_C0OAR_VALUE (0xFFFF)
308 #define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
309 #define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
310 #define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
311 #define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
312 #define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
313 #define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
314 #define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
315 #define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
316 #define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
317 #define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
318 #define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
319 #define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
320 #define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
321 #define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
322 #define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
323 #define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
324 /* Clock activity observability register 1 */
325 #define U300_SYSCON_C1OAR (0x144)
326 #define U300_SYSCON_C1OAR_MASK (0x3FFE)
327 #define U300_SYSCON_C1OAR_VALUE (0x3FFE)
328 #define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
329 #define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
330 #define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
331 #define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
332 #define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
333 #define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
334 #define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
335 #define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
336 #define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
337 #define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
338 #define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
339 #define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
340 #define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
341 /* Clock activity observability register 2 */
342 #define U300_SYSCON_C2OAR (0x148)
343 #define U300_SYSCON_C2OAR_MASK (0x0FFF)
344 #define U300_SYSCON_C2OAR_VALUE (0x0FFF)
345 #define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
346 #define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
347 #define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
348 #define U300_SYSCON_C2OAR_VC_CLK (0x0100)
349 #define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
350 #define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
351 #define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
352 #define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
353 #define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
354 #define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
355 #define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
356 #define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
357
358
359 /*
360 * The clocking hierarchy currently looks like this.
361 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
362 * The ideas is to show dependencies, so a clock higher up in the
363 * hierarchy has to be on in order for another clock to be on. Now,
364 * both CPU and DMA can actually be on top of the hierarchy, and that
365 * is not modeled currently. Instead we have the backbone AMBA bus on
366 * top. This bus cannot be programmed in any way but conceptually it
367 * needs to be active for the bridges and devices to transport data.
368 *
369 * Please be aware that a few clocks are hw controlled, which mean that
370 * the hw itself can turn on/off or change the rate of the clock when
371 * needed!
372 *
373 * AMBA bus
374 * |
375 * +- CPU
376 * +- FSMC NANDIF NAND Flash interface
377 * +- SEMI Shared Memory interface
378 * +- ISP Image Signal Processor (U335 only)
379 * +- CDS (U335 only)
380 * +- DMA Direct Memory Access Controller
381 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
382 * +- APEX
383 * +- VIDEO_ENC AVE2/3 Video Encoder
384 * +- XGAM Graphics Accelerator Controller
385 * +- AHB
386 * |
387 * +- ahb:0 AHB Bridge
388 * | |
389 * | +- ahb:1 INTCON Interrupt controller
390 * | +- ahb:3 MSPRO Memory Stick Pro controller
391 * | +- ahb:4 EMIF External Memory interface
392 * |
393 * +- fast:0 FAST bridge
394 * | |
395 * | +- fast:1 MMCSD MMC/SD card reader controller
396 * | +- fast:2 I2S0 PCM I2S channel 0 controller
397 * | +- fast:3 I2S1 PCM I2S channel 1 controller
398 * | +- fast:4 I2C0 I2C channel 0 controller
399 * | +- fast:5 I2C1 I2C channel 1 controller
400 * | +- fast:6 SPI SPI controller
401 * | +- fast:7 UART1 Secondary UART (U335 only)
402 * |
403 * +- slow:0 SLOW bridge
404 * |
405 * +- slow:1 SYSCON (not possible to control)
406 * +- slow:2 WDOG Watchdog
407 * +- slow:3 UART0 primary UART
408 * +- slow:4 TIMER_APP Application timer - used in Linux
409 * +- slow:5 KEYPAD controller
410 * +- slow:6 GPIO controller
411 * +- slow:7 RTC controller
412 * +- slow:8 BT Bus Tracer (not used currently)
413 * +- slow:9 EH Event Handler (not used currently)
414 * +- slow:a TIMER_ACC Access style timer (not used currently)
415 * +- slow:b PPM (U335 only, what is that?)
416 */
417
418 /* Global syscon virtual base */
419 static void __iomem *syscon_vbase;
420
421 /**
422 * struct clk_syscon - U300 syscon clock
423 * @hw: corresponding clock hardware entry
424 * @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
425 * and does not need any magic pokes to be enabled/disabled
426 * @reset: state holder, whether this block's reset line is asserted or not
427 * @res_reg: reset line enable/disable flag register
428 * @res_bit: bit for resetting or taking this consumer out of reset
429 * @en_reg: clock line enable/disable flag register
430 * @en_bit: bit for enabling/disabling this consumer clock line
431 * @clk_val: magic value to poke in the register to enable/disable
432 * this one clock
433 */
434 struct clk_syscon {
435 struct clk_hw hw;
436 bool hw_ctrld;
437 bool reset;
438 void __iomem *res_reg;
439 u8 res_bit;
440 void __iomem *en_reg;
441 u8 en_bit;
442 u16 clk_val;
443 };
444
445 #define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
446
447 static DEFINE_SPINLOCK(syscon_resetreg_lock);
448
449 /*
450 * Reset control functions. We remember if a block has been
451 * taken out of reset and don't remove the reset assertion again
452 * and vice versa. Currently we only remove resets so the
453 * enablement function is defined out.
454 */
syscon_block_reset_enable(struct clk_syscon * sclk)455 static void syscon_block_reset_enable(struct clk_syscon *sclk)
456 {
457 unsigned long iflags;
458 u16 val;
459
460 /* Not all blocks support resetting */
461 if (!sclk->res_reg)
462 return;
463 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
464 val = readw(sclk->res_reg);
465 val |= BIT(sclk->res_bit);
466 writew(val, sclk->res_reg);
467 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
468 sclk->reset = true;
469 }
470
syscon_block_reset_disable(struct clk_syscon * sclk)471 static void syscon_block_reset_disable(struct clk_syscon *sclk)
472 {
473 unsigned long iflags;
474 u16 val;
475
476 /* Not all blocks support resetting */
477 if (!sclk->res_reg)
478 return;
479 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
480 val = readw(sclk->res_reg);
481 val &= ~BIT(sclk->res_bit);
482 writew(val, sclk->res_reg);
483 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
484 sclk->reset = false;
485 }
486
syscon_clk_prepare(struct clk_hw * hw)487 static int syscon_clk_prepare(struct clk_hw *hw)
488 {
489 struct clk_syscon *sclk = to_syscon(hw);
490
491 /* If the block is in reset, bring it out */
492 if (sclk->reset)
493 syscon_block_reset_disable(sclk);
494 return 0;
495 }
496
syscon_clk_unprepare(struct clk_hw * hw)497 static void syscon_clk_unprepare(struct clk_hw *hw)
498 {
499 struct clk_syscon *sclk = to_syscon(hw);
500
501 /* Please don't force the console into reset */
502 if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
503 return;
504 /* When unpreparing, force block into reset */
505 if (!sclk->reset)
506 syscon_block_reset_enable(sclk);
507 }
508
syscon_clk_enable(struct clk_hw * hw)509 static int syscon_clk_enable(struct clk_hw *hw)
510 {
511 struct clk_syscon *sclk = to_syscon(hw);
512
513 /* Don't touch the hardware controlled clocks */
514 if (sclk->hw_ctrld)
515 return 0;
516 /* These cannot be controlled */
517 if (sclk->clk_val == 0xFFFFU)
518 return 0;
519
520 writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
521 return 0;
522 }
523
syscon_clk_disable(struct clk_hw * hw)524 static void syscon_clk_disable(struct clk_hw *hw)
525 {
526 struct clk_syscon *sclk = to_syscon(hw);
527
528 /* Don't touch the hardware controlled clocks */
529 if (sclk->hw_ctrld)
530 return;
531 if (sclk->clk_val == 0xFFFFU)
532 return;
533 /* Please don't disable the console port */
534 if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
535 return;
536
537 writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
538 }
539
syscon_clk_is_enabled(struct clk_hw * hw)540 static int syscon_clk_is_enabled(struct clk_hw *hw)
541 {
542 struct clk_syscon *sclk = to_syscon(hw);
543 u16 val;
544
545 /* If no enable register defined, it's always-on */
546 if (!sclk->en_reg)
547 return 1;
548
549 val = readw(sclk->en_reg);
550 val &= BIT(sclk->en_bit);
551
552 return val ? 1 : 0;
553 }
554
syscon_get_perf(void)555 static u16 syscon_get_perf(void)
556 {
557 u16 val;
558
559 val = readw(syscon_vbase + U300_SYSCON_CCR);
560 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
561 return val;
562 }
563
564 static unsigned long
syscon_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)565 syscon_clk_recalc_rate(struct clk_hw *hw,
566 unsigned long parent_rate)
567 {
568 struct clk_syscon *sclk = to_syscon(hw);
569 u16 perf = syscon_get_perf();
570
571 switch(sclk->clk_val) {
572 case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
573 case U300_SYSCON_SBCER_I2C0_CLK_EN:
574 case U300_SYSCON_SBCER_I2C1_CLK_EN:
575 case U300_SYSCON_SBCER_MMC_CLK_EN:
576 case U300_SYSCON_SBCER_SPI_CLK_EN:
577 /* The FAST clocks have one progression */
578 switch(perf) {
579 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
580 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
581 return 13000000;
582 default:
583 return parent_rate; /* 26 MHz */
584 }
585 case U300_SYSCON_SBCER_DMAC_CLK_EN:
586 case U300_SYSCON_SBCER_NANDIF_CLK_EN:
587 case U300_SYSCON_SBCER_XGAM_CLK_EN:
588 /* AMBA interconnect peripherals */
589 switch(perf) {
590 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
592 return 6500000;
593 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
594 return 26000000;
595 default:
596 return parent_rate; /* 52 MHz */
597 }
598 case U300_SYSCON_SBCER_SEMI_CLK_EN:
599 case U300_SYSCON_SBCER_EMIF_CLK_EN:
600 /* EMIF speeds */
601 switch(perf) {
602 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
603 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
604 return 13000000;
605 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
606 return 52000000;
607 default:
608 return 104000000;
609 }
610 case U300_SYSCON_SBCER_CPU_CLK_EN:
611 /* And the fast CPU clock */
612 switch(perf) {
613 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
614 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
615 return 13000000;
616 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
617 return 52000000;
618 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
619 return 104000000;
620 default:
621 return parent_rate; /* 208 MHz */
622 }
623 default:
624 /*
625 * The SLOW clocks and default just inherit the rate of
626 * their parent (typically PLL13 13 MHz).
627 */
628 return parent_rate;
629 }
630 }
631
632 static long
syscon_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)633 syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
634 unsigned long *prate)
635 {
636 struct clk_syscon *sclk = to_syscon(hw);
637
638 if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
639 return *prate;
640 /* We really only support setting the rate of the CPU clock */
641 if (rate <= 13000000)
642 return 13000000;
643 if (rate <= 52000000)
644 return 52000000;
645 if (rate <= 104000000)
646 return 104000000;
647 return 208000000;
648 }
649
syscon_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)650 static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate,
651 unsigned long parent_rate)
652 {
653 struct clk_syscon *sclk = to_syscon(hw);
654 u16 val;
655
656 /* We only support setting the rate of the CPU clock */
657 if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
658 return -EINVAL;
659 switch (rate) {
660 case 13000000:
661 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
662 break;
663 case 52000000:
664 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
665 break;
666 case 104000000:
667 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
668 break;
669 case 208000000:
670 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
671 break;
672 default:
673 return -EINVAL;
674 }
675 val |= readw(syscon_vbase + U300_SYSCON_CCR) &
676 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
677 writew(val, syscon_vbase + U300_SYSCON_CCR);
678 return 0;
679 }
680
681 static const struct clk_ops syscon_clk_ops = {
682 .prepare = syscon_clk_prepare,
683 .unprepare = syscon_clk_unprepare,
684 .enable = syscon_clk_enable,
685 .disable = syscon_clk_disable,
686 .is_enabled = syscon_clk_is_enabled,
687 .recalc_rate = syscon_clk_recalc_rate,
688 .round_rate = syscon_clk_round_rate,
689 .set_rate = syscon_clk_set_rate,
690 };
691
692 static struct clk * __init
syscon_clk_register(struct device * dev,const char * name,const char * parent_name,unsigned long flags,bool hw_ctrld,void __iomem * res_reg,u8 res_bit,void __iomem * en_reg,u8 en_bit,u16 clk_val)693 syscon_clk_register(struct device *dev, const char *name,
694 const char *parent_name, unsigned long flags,
695 bool hw_ctrld,
696 void __iomem *res_reg, u8 res_bit,
697 void __iomem *en_reg, u8 en_bit,
698 u16 clk_val)
699 {
700 struct clk *clk;
701 struct clk_syscon *sclk;
702 struct clk_init_data init;
703
704 sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL);
705 if (!sclk) {
706 pr_err("could not allocate syscon clock %s\n",
707 name);
708 return ERR_PTR(-ENOMEM);
709 }
710 init.name = name;
711 init.ops = &syscon_clk_ops;
712 init.flags = flags;
713 init.parent_names = (parent_name ? &parent_name : NULL);
714 init.num_parents = (parent_name ? 1 : 0);
715 sclk->hw.init = &init;
716 sclk->hw_ctrld = hw_ctrld;
717 /* Assume the block is in reset at registration */
718 sclk->reset = true;
719 sclk->res_reg = res_reg;
720 sclk->res_bit = res_bit;
721 sclk->en_reg = en_reg;
722 sclk->en_bit = en_bit;
723 sclk->clk_val = clk_val;
724
725 clk = clk_register(dev, &sclk->hw);
726 if (IS_ERR(clk))
727 kfree(sclk);
728
729 return clk;
730 }
731
732 #define U300_CLK_TYPE_SLOW 0
733 #define U300_CLK_TYPE_FAST 1
734 #define U300_CLK_TYPE_REST 2
735
736 /**
737 * struct u300_clock - defines the bits and pieces for a certain clock
738 * @type: the clock type, slow fast or rest
739 * @id: the bit in the slow/fast/rest register for this clock
740 * @hw_ctrld: whether the clock is hardware controlled
741 * @clk_val: a value to poke in the one-write enable/disable registers
742 */
743 struct u300_clock {
744 u8 type;
745 u8 id;
746 bool hw_ctrld;
747 u16 clk_val;
748 };
749
750 static struct u300_clock const u300_clk_lookup[] __initconst = {
751 {
752 .type = U300_CLK_TYPE_REST,
753 .id = 3,
754 .hw_ctrld = true,
755 .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
756 },
757 {
758 .type = U300_CLK_TYPE_REST,
759 .id = 4,
760 .hw_ctrld = true,
761 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
762 },
763 {
764 .type = U300_CLK_TYPE_REST,
765 .id = 5,
766 .hw_ctrld = false,
767 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
768 },
769 {
770 .type = U300_CLK_TYPE_REST,
771 .id = 6,
772 .hw_ctrld = false,
773 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
774 },
775 {
776 .type = U300_CLK_TYPE_REST,
777 .id = 8,
778 .hw_ctrld = true,
779 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
780 },
781 {
782 .type = U300_CLK_TYPE_REST,
783 .id = 9,
784 .hw_ctrld = false,
785 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
786 },
787 {
788 .type = U300_CLK_TYPE_REST,
789 .id = 10,
790 .hw_ctrld = true,
791 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
792 },
793 {
794 .type = U300_CLK_TYPE_REST,
795 .id = 12,
796 .hw_ctrld = false,
797 /* INTCON: cannot be enabled, just taken out of reset */
798 .clk_val = 0xFFFFU,
799 },
800 {
801 .type = U300_CLK_TYPE_FAST,
802 .id = 0,
803 .hw_ctrld = true,
804 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
805 },
806 {
807 .type = U300_CLK_TYPE_FAST,
808 .id = 1,
809 .hw_ctrld = false,
810 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
811 },
812 {
813 .type = U300_CLK_TYPE_FAST,
814 .id = 2,
815 .hw_ctrld = false,
816 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
817 },
818 {
819 .type = U300_CLK_TYPE_FAST,
820 .id = 5,
821 .hw_ctrld = false,
822 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
823 },
824 {
825 .type = U300_CLK_TYPE_FAST,
826 .id = 6,
827 .hw_ctrld = false,
828 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
829 },
830 {
831 .type = U300_CLK_TYPE_SLOW,
832 .id = 0,
833 .hw_ctrld = true,
834 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
835 },
836 {
837 .type = U300_CLK_TYPE_SLOW,
838 .id = 1,
839 .hw_ctrld = false,
840 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
841 },
842 {
843 .type = U300_CLK_TYPE_SLOW,
844 .id = 4,
845 .hw_ctrld = false,
846 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
847 },
848 {
849 .type = U300_CLK_TYPE_SLOW,
850 .id = 6,
851 .hw_ctrld = true,
852 /* No clock enable register bit */
853 .clk_val = 0xFFFFU,
854 },
855 {
856 .type = U300_CLK_TYPE_SLOW,
857 .id = 7,
858 .hw_ctrld = false,
859 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
860 },
861 {
862 .type = U300_CLK_TYPE_SLOW,
863 .id = 8,
864 .hw_ctrld = false,
865 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
866 },
867 };
868
of_u300_syscon_clk_init(struct device_node * np)869 static void __init of_u300_syscon_clk_init(struct device_node *np)
870 {
871 struct clk *clk = ERR_PTR(-EINVAL);
872 const char *clk_name = np->name;
873 const char *parent_name;
874 void __iomem *res_reg;
875 void __iomem *en_reg;
876 u32 clk_type;
877 u32 clk_id;
878 int i;
879
880 if (of_property_read_u32(np, "clock-type", &clk_type)) {
881 pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
882 __func__, clk_name);
883 return;
884 }
885 if (of_property_read_u32(np, "clock-id", &clk_id)) {
886 pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
887 __func__, clk_name);
888 return;
889 }
890 parent_name = of_clk_get_parent_name(np, 0);
891
892 switch (clk_type) {
893 case U300_CLK_TYPE_SLOW:
894 res_reg = syscon_vbase + U300_SYSCON_RSR;
895 en_reg = syscon_vbase + U300_SYSCON_CESR;
896 break;
897 case U300_CLK_TYPE_FAST:
898 res_reg = syscon_vbase + U300_SYSCON_RFR;
899 en_reg = syscon_vbase + U300_SYSCON_CEFR;
900 break;
901 case U300_CLK_TYPE_REST:
902 res_reg = syscon_vbase + U300_SYSCON_RRR;
903 en_reg = syscon_vbase + U300_SYSCON_CERR;
904 break;
905 default:
906 pr_err("unknown clock type %x specified\n", clk_type);
907 return;
908 }
909
910 for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
911 const struct u300_clock *u3clk = &u300_clk_lookup[i];
912
913 if (u3clk->type == clk_type && u3clk->id == clk_id)
914 clk = syscon_clk_register(NULL,
915 clk_name, parent_name,
916 0, u3clk->hw_ctrld,
917 res_reg, u3clk->id,
918 en_reg, u3clk->id,
919 u3clk->clk_val);
920 }
921
922 if (!IS_ERR(clk)) {
923 of_clk_add_provider(np, of_clk_src_simple_get, clk);
924
925 /*
926 * Some few system clocks - device tree does not
927 * represent clocks without a corresponding device node.
928 * for now we add these three clocks here.
929 */
930 if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
931 clk_register_clkdev(clk, NULL, "pl172");
932 if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
933 clk_register_clkdev(clk, NULL, "semi");
934 if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
935 clk_register_clkdev(clk, NULL, "intcon");
936 }
937 }
938
939 /**
940 * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
941 * @hw: corresponding clock hardware entry
942 * @is_mspro: if this is the memory stick clock rather than MMC/SD
943 */
944 struct clk_mclk {
945 struct clk_hw hw;
946 bool is_mspro;
947 };
948
949 #define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw)
950
mclk_clk_prepare(struct clk_hw * hw)951 static int mclk_clk_prepare(struct clk_hw *hw)
952 {
953 struct clk_mclk *mclk = to_mclk(hw);
954 u16 val;
955
956 /* The MMC and MSPRO clocks need some special set-up */
957 if (!mclk->is_mspro) {
958 /* Set default MMC clock divisor to 18.9 MHz */
959 writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);
960 val = readw(syscon_vbase + U300_SYSCON_MMCR);
961 /* Disable the MMC feedback clock */
962 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
963 /* Disable MSPRO frequency */
964 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
965 writew(val, syscon_vbase + U300_SYSCON_MMCR);
966 } else {
967 val = readw(syscon_vbase + U300_SYSCON_MMCR);
968 /* Disable the MMC feedback clock */
969 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
970 /* Enable MSPRO frequency */
971 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
972 writew(val, syscon_vbase + U300_SYSCON_MMCR);
973 }
974
975 return 0;
976 }
977
978 static unsigned long
mclk_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)979 mclk_clk_recalc_rate(struct clk_hw *hw,
980 unsigned long parent_rate)
981 {
982 u16 perf = syscon_get_perf();
983
984 switch (perf) {
985 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
986 /*
987 * Here, the 208 MHz PLL gets shut down and the always
988 * on 13 MHz PLL used for RTC etc kicks into use
989 * instead.
990 */
991 return 13000000;
992 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
993 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
994 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
995 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
996 {
997 /*
998 * This clock is under program control. The register is
999 * divided in two nybbles, bit 7-4 gives cycles-1 to count
1000 * high, bit 3-0 gives cycles-1 to count low. Distribute
1001 * these with no more than 1 cycle difference between
1002 * low and high and add low and high to get the actual
1003 * divisor. The base PLL is 208 MHz. Writing 0x00 will
1004 * divide by 1 and 1 so the highest frequency possible
1005 * is 104 MHz.
1006 *
1007 * e.g. 0x54 =>
1008 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
1009 */
1010 u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
1011 U300_SYSCON_MMF0R_MASK;
1012 switch (val) {
1013 case 0x0054:
1014 return 18900000;
1015 case 0x0044:
1016 return 20800000;
1017 case 0x0043:
1018 return 23100000;
1019 case 0x0033:
1020 return 26000000;
1021 case 0x0032:
1022 return 29700000;
1023 case 0x0022:
1024 return 34700000;
1025 case 0x0021:
1026 return 41600000;
1027 case 0x0011:
1028 return 52000000;
1029 case 0x0000:
1030 return 104000000;
1031 default:
1032 break;
1033 }
1034 }
1035 default:
1036 break;
1037 }
1038 return parent_rate;
1039 }
1040
1041 static long
mclk_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1042 mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1043 unsigned long *prate)
1044 {
1045 if (rate <= 18900000)
1046 return 18900000;
1047 if (rate <= 20800000)
1048 return 20800000;
1049 if (rate <= 23100000)
1050 return 23100000;
1051 if (rate <= 26000000)
1052 return 26000000;
1053 if (rate <= 29700000)
1054 return 29700000;
1055 if (rate <= 34700000)
1056 return 34700000;
1057 if (rate <= 41600000)
1058 return 41600000;
1059 /* Highest rate */
1060 return 52000000;
1061 }
1062
mclk_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1063 static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1064 unsigned long parent_rate)
1065 {
1066 u16 val;
1067 u16 reg;
1068
1069 switch (rate) {
1070 case 18900000:
1071 val = 0x0054;
1072 break;
1073 case 20800000:
1074 val = 0x0044;
1075 break;
1076 case 23100000:
1077 val = 0x0043;
1078 break;
1079 case 26000000:
1080 val = 0x0033;
1081 break;
1082 case 29700000:
1083 val = 0x0032;
1084 break;
1085 case 34700000:
1086 val = 0x0022;
1087 break;
1088 case 41600000:
1089 val = 0x0021;
1090 break;
1091 case 52000000:
1092 val = 0x0011;
1093 break;
1094 case 104000000:
1095 val = 0x0000;
1096 break;
1097 default:
1098 return -EINVAL;
1099 }
1100
1101 reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &
1102 ~U300_SYSCON_MMF0R_MASK;
1103 writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
1104 return 0;
1105 }
1106
1107 static const struct clk_ops mclk_ops = {
1108 .prepare = mclk_clk_prepare,
1109 .recalc_rate = mclk_clk_recalc_rate,
1110 .round_rate = mclk_clk_round_rate,
1111 .set_rate = mclk_clk_set_rate,
1112 };
1113
1114 static struct clk * __init
mclk_clk_register(struct device * dev,const char * name,const char * parent_name,bool is_mspro)1115 mclk_clk_register(struct device *dev, const char *name,
1116 const char *parent_name, bool is_mspro)
1117 {
1118 struct clk *clk;
1119 struct clk_mclk *mclk;
1120 struct clk_init_data init;
1121
1122 mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL);
1123 if (!mclk) {
1124 pr_err("could not allocate MMC/SD clock %s\n",
1125 name);
1126 return ERR_PTR(-ENOMEM);
1127 }
1128 init.name = "mclk";
1129 init.ops = &mclk_ops;
1130 init.flags = 0;
1131 init.parent_names = (parent_name ? &parent_name : NULL);
1132 init.num_parents = (parent_name ? 1 : 0);
1133 mclk->hw.init = &init;
1134 mclk->is_mspro = is_mspro;
1135
1136 clk = clk_register(dev, &mclk->hw);
1137 if (IS_ERR(clk))
1138 kfree(mclk);
1139
1140 return clk;
1141 }
1142
of_u300_syscon_mclk_init(struct device_node * np)1143 static void __init of_u300_syscon_mclk_init(struct device_node *np)
1144 {
1145 struct clk *clk = ERR_PTR(-EINVAL);
1146 const char *clk_name = np->name;
1147 const char *parent_name;
1148
1149 parent_name = of_clk_get_parent_name(np, 0);
1150 clk = mclk_clk_register(NULL, clk_name, parent_name, false);
1151 if (!IS_ERR(clk))
1152 of_clk_add_provider(np, of_clk_src_simple_get, clk);
1153 }
1154
1155 static const struct of_device_id u300_clk_match[] __initconst = {
1156 {
1157 .compatible = "fixed-clock",
1158 .data = of_fixed_clk_setup,
1159 },
1160 {
1161 .compatible = "fixed-factor-clock",
1162 .data = of_fixed_factor_clk_setup,
1163 },
1164 {
1165 .compatible = "stericsson,u300-syscon-clk",
1166 .data = of_u300_syscon_clk_init,
1167 },
1168 {
1169 .compatible = "stericsson,u300-syscon-mclk",
1170 .data = of_u300_syscon_mclk_init,
1171 },
1172 {}
1173 };
1174
1175
u300_clk_init(void __iomem * base)1176 void __init u300_clk_init(void __iomem *base)
1177 {
1178 u16 val;
1179
1180 syscon_vbase = base;
1181
1182 /* Set system to run at PLL208, max performance, a known state. */
1183 val = readw(syscon_vbase + U300_SYSCON_CCR);
1184 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1185 writew(val, syscon_vbase + U300_SYSCON_CCR);
1186 /* Wait for the PLL208 to lock if not locked in yet */
1187 while (!(readw(syscon_vbase + U300_SYSCON_CSR) &
1188 U300_SYSCON_CSR_PLL208_LOCK_IND));
1189
1190 /* Power management enable */
1191 val = readw(syscon_vbase + U300_SYSCON_PMCR);
1192 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1193 writew(val, syscon_vbase + U300_SYSCON_PMCR);
1194
1195 of_clk_init(u300_clk_match);
1196 }
1197