1/*
2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/irqdomain.h>
14#include <linux/irqchip.h>
15#include "../../drivers/irqchip/irqchip.h"
16#include <asm/sections.h>
17#include <asm/irq.h>
18#include <asm/mach_desc.h>
19
20/*
21 * Early Hardware specific Interrupt setup
22 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
23 * -Called very early (start_kernel -> setup_arch -> setup_processor)
24 *
25 * what it does ?
26 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
27 */
28void arc_init_IRQ(void)
29{
30	int level_mask = 0;
31
32       /* setup any high priority Interrupts (Level2 in ARCompact jargon) */
33	level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
34	level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
35	level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
36
37	/*
38	 * Write to register, even if no LV2 IRQs configured to reset it
39	 * in case bootloader had mucked with it
40	 */
41	write_aux_reg(AUX_IRQ_LEV, level_mask);
42
43	if (level_mask)
44		pr_info("Level-2 interrupts bitset %x\n", level_mask);
45}
46
47/*
48 * ARC700 core includes a simple on-chip intc supporting
49 * -per IRQ enable/disable
50 * -2 levels of interrupts (high/low)
51 * -all interrupts being level triggered
52 *
53 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
54 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
55 * below, per IRQ.
56 */
57
58static void arc_irq_mask(struct irq_data *data)
59{
60	unsigned int ienb;
61
62	ienb = read_aux_reg(AUX_IENABLE);
63	ienb &= ~(1 << data->irq);
64	write_aux_reg(AUX_IENABLE, ienb);
65}
66
67static void arc_irq_unmask(struct irq_data *data)
68{
69	unsigned int ienb;
70
71	ienb = read_aux_reg(AUX_IENABLE);
72	ienb |= (1 << data->irq);
73	write_aux_reg(AUX_IENABLE, ienb);
74}
75
76static struct irq_chip onchip_intc = {
77	.name           = "ARC In-core Intc",
78	.irq_mask	= arc_irq_mask,
79	.irq_unmask	= arc_irq_unmask,
80};
81
82static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
83				irq_hw_number_t hw)
84{
85	if (irq == TIMER0_IRQ)
86		irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
87	else
88		irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
89
90	return 0;
91}
92
93static const struct irq_domain_ops arc_intc_domain_ops = {
94	.xlate = irq_domain_xlate_onecell,
95	.map = arc_intc_domain_map,
96};
97
98static struct irq_domain *root_domain;
99
100static int __init
101init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
102{
103	if (parent)
104		panic("DeviceTree incore intc not a root irq controller\n");
105
106	root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
107					    &arc_intc_domain_ops, NULL);
108
109	if (!root_domain)
110		panic("root irq domain not avail\n");
111
112	/* with this we don't need to export root_domain */
113	irq_set_default_host(root_domain);
114
115	return 0;
116}
117
118IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
119
120/*
121 * Late Interrupt system init called from start_kernel for Boot CPU only
122 *
123 * Since slab must already be initialized, platforms can start doing any
124 * needed request_irq( )s
125 */
126void __init init_IRQ(void)
127{
128	/* Any external intc can be setup here */
129	if (machine_desc->init_irq)
130		machine_desc->init_irq();
131
132	/* process the entire interrupt tree in one go */
133	irqchip_init();
134
135#ifdef CONFIG_SMP
136	/* Master CPU can initialize it's side of IPI */
137	if (machine_desc->init_smp)
138		machine_desc->init_smp(smp_processor_id());
139#endif
140}
141
142/*
143 * "C" Entry point for any ARC ISR, called from low level vector handler
144 * @irq is the vector number read from ICAUSE reg of on-chip intc
145 */
146void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
147{
148	struct pt_regs *old_regs = set_irq_regs(regs);
149
150	irq_enter();
151	generic_handle_irq(irq);
152	irq_exit();
153	set_irq_regs(old_regs);
154}
155
156void arc_request_percpu_irq(int irq, int cpu,
157                            irqreturn_t (*isr)(int irq, void *dev),
158                            const char *irq_nm,
159                            void *percpu_dev)
160{
161	/* Boot cpu calls request, all call enable */
162	if (!cpu) {
163		int rc;
164
165		/*
166		 * These 2 calls are essential to making percpu IRQ APIs work
167		 * Ideally these details could be hidden in irq chip map function
168		 * but the issue is IPIs IRQs being static (non-DT) and platform
169		 * specific, so we can't identify them there.
170		 */
171		irq_set_percpu_devid(irq);
172		irq_modify_status(irq, IRQ_NOAUTOEN, 0);  /* @irq, @clr, @set */
173
174		rc = request_percpu_irq(irq, isr, irq_nm, percpu_dev);
175		if (rc)
176			panic("Percpu IRQ request failed for %d\n", irq);
177	}
178
179	enable_percpu_irq(irq, 0);
180}
181
182/*
183 * arch_local_irq_enable - Enable interrupts.
184 *
185 * 1. Explicitly called to re-enable interrupts
186 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
187 *    which maybe in hard ISR itself
188 *
189 * Semantics of this function change depending on where it is called from:
190 *
191 * -If called from hard-ISR, it must not invert interrupt priorities
192 *  e.g. suppose TIMER is high priority (Level 2) IRQ
193 *    Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
194 *    Here local_irq_enable( ) shd not re-enable lower priority interrupts
195 * -If called from soft-ISR, it must re-enable all interrupts
196 *    soft ISR are low prioity jobs which can be very slow, thus all IRQs
197 *    must be enabled while they run.
198 *    Now hardware context wise we may still be in L2 ISR (not done rtie)
199 *    still we must re-enable both L1 and L2 IRQs
200 *  Another twist is prev scenario with flow being
201 *     L1 ISR ==> interrupted by L2 ISR  ==> L2 soft ISR
202 *     here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
203 *     over-written (this is deficiency in ARC700 Interrupt mechanism)
204 */
205
206#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS	/* Complex version for 2 IRQ levels */
207
208void arch_local_irq_enable(void)
209{
210
211	unsigned long flags;
212	flags = arch_local_save_flags();
213
214	/* Allow both L1 and L2 at the onset */
215	flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
216
217	/* Called from hard ISR (between irq_enter and irq_exit) */
218	if (in_irq()) {
219
220		/* If in L2 ISR, don't re-enable any further IRQs as this can
221		 * cause IRQ priorities to get upside down. e.g. it could allow
222		 * L1 be taken while in L2 hard ISR which is wrong not only in
223		 * theory, it can also cause the dreaded L1-L2-L1 scenario
224		 */
225		if (flags & STATUS_A2_MASK)
226			flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
227
228		/* Even if in L1 ISR, allowe Higher prio L2 IRQs */
229		else if (flags & STATUS_A1_MASK)
230			flags &= ~(STATUS_E1_MASK);
231	}
232
233	/* called from soft IRQ, ideally we want to re-enable all levels */
234
235	else if (in_softirq()) {
236
237		/* However if this is case of L1 interrupted by L2,
238		 * re-enabling both may cause whaco L1-L2-L1 scenario
239		 * because ARC700 allows level 1 to interrupt an active L2 ISR
240		 * Thus we disable both
241		 * However some code, executing in soft ISR wants some IRQs
242		 * to be enabled so we re-enable L2 only
243		 *
244		 * How do we determine L1 intr by L2
245		 *  -A2 is set (means in L2 ISR)
246		 *  -E1 is set in this ISR's pt_regs->status32 which is
247		 *      saved copy of status32_l2 when l2 ISR happened
248		 */
249		struct pt_regs *pt = get_irq_regs();
250		if ((flags & STATUS_A2_MASK) && pt &&
251		    (pt->status32 & STATUS_A1_MASK)) {
252			/*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
253			flags &= ~(STATUS_E1_MASK);
254		}
255	}
256
257	arch_local_irq_restore(flags);
258}
259
260#else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
261
262/*
263 * Simpler version for only 1 level of interrupt
264 * Here we only Worry about Level 1 Bits
265 */
266void arch_local_irq_enable(void)
267{
268	unsigned long flags;
269
270	/*
271	 * ARC IDE Drivers tries to re-enable interrupts from hard-isr
272	 * context which is simply wrong
273	 */
274	if (in_irq()) {
275		WARN_ONCE(1, "IRQ enabled from hard-isr");
276		return;
277	}
278
279	flags = arch_local_save_flags();
280	flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
281	arch_local_irq_restore(flags);
282}
283#endif
284EXPORT_SYMBOL(arch_local_irq_enable);
285