1/* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20#include <linux/module.h> 21#include <linux/irq.h> 22#include <linux/irqdomain.h> 23#include <linux/io.h> 24#include <linux/of.h> 25#include <asm/mach/irq.h> 26#include <asm/exception.h> 27 28#include "common.h" 29#include "hardware.h" 30#include "irq-common.h" 31 32#define AVIC_INTCNTL 0x00 /* int control reg */ 33#define AVIC_NIMASK 0x04 /* int mask reg */ 34#define AVIC_INTENNUM 0x08 /* int enable number reg */ 35#define AVIC_INTDISNUM 0x0C /* int disable number reg */ 36#define AVIC_INTENABLEH 0x10 /* int enable reg high */ 37#define AVIC_INTENABLEL 0x14 /* int enable reg low */ 38#define AVIC_INTTYPEH 0x18 /* int type reg high */ 39#define AVIC_INTTYPEL 0x1C /* int type reg low */ 40#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ 41#define AVIC_NIVECSR 0x40 /* norm int vector/status */ 42#define AVIC_FIVECSR 0x44 /* fast int vector/status */ 43#define AVIC_INTSRCH 0x48 /* int source reg high */ 44#define AVIC_INTSRCL 0x4C /* int source reg low */ 45#define AVIC_INTFRCH 0x50 /* int force reg high */ 46#define AVIC_INTFRCL 0x54 /* int force reg low */ 47#define AVIC_NIPNDH 0x58 /* norm int pending high */ 48#define AVIC_NIPNDL 0x5C /* norm int pending low */ 49#define AVIC_FIPNDH 0x60 /* fast int pending high */ 50#define AVIC_FIPNDL 0x64 /* fast int pending low */ 51 52#define AVIC_NUM_IRQS 64 53 54static void __iomem *avic_base; 55static struct irq_domain *domain; 56 57#ifdef CONFIG_FIQ 58static int avic_set_irq_fiq(unsigned int irq, unsigned int type) 59{ 60 struct irq_data *d = irq_get_irq_data(irq); 61 unsigned int irqt; 62 63 irq = d->hwirq; 64 65 if (irq >= AVIC_NUM_IRQS) 66 return -EINVAL; 67 68 if (irq < AVIC_NUM_IRQS / 2) { 69 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); 70 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); 71 } else { 72 irq -= AVIC_NUM_IRQS / 2; 73 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); 74 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); 75 } 76 77 return 0; 78} 79#endif /* CONFIG_FIQ */ 80 81 82static struct mxc_extra_irq avic_extra_irq = { 83#ifdef CONFIG_FIQ 84 .set_irq_fiq = avic_set_irq_fiq, 85#endif 86}; 87 88#ifdef CONFIG_PM 89static u32 avic_saved_mask_reg[2]; 90 91static void avic_irq_suspend(struct irq_data *d) 92{ 93 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 94 struct irq_chip_type *ct = gc->chip_types; 95 int idx = d->hwirq >> 5; 96 97 avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); 98 __raw_writel(gc->wake_active, avic_base + ct->regs.mask); 99} 100 101static void avic_irq_resume(struct irq_data *d) 102{ 103 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 104 struct irq_chip_type *ct = gc->chip_types; 105 int idx = d->hwirq >> 5; 106 107 __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); 108} 109 110#else 111#define avic_irq_suspend NULL 112#define avic_irq_resume NULL 113#endif 114 115static __init void avic_init_gc(int idx, unsigned int irq_start) 116{ 117 struct irq_chip_generic *gc; 118 struct irq_chip_type *ct; 119 120 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, 121 handle_level_irq); 122 gc->private = &avic_extra_irq; 123 gc->wake_enabled = IRQ_MSK(32); 124 125 ct = gc->chip_types; 126 ct->chip.irq_mask = irq_gc_mask_clr_bit; 127 ct->chip.irq_unmask = irq_gc_mask_set_bit; 128 ct->chip.irq_ack = irq_gc_mask_clr_bit; 129 ct->chip.irq_set_wake = irq_gc_set_wake; 130 ct->chip.irq_suspend = avic_irq_suspend; 131 ct->chip.irq_resume = avic_irq_resume; 132 ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; 133 ct->regs.ack = ct->regs.mask; 134 135 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 136} 137 138static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) 139{ 140 u32 nivector; 141 142 do { 143 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16; 144 if (nivector == 0xffff) 145 break; 146 147 handle_domain_irq(domain, nivector, regs); 148 } while (1); 149} 150 151/* 152 * This function initializes the AVIC hardware and disables all the 153 * interrupts. It registers the interrupt enable and disable functions 154 * to the kernel for each interrupt source. 155 */ 156void __init mxc_init_irq(void __iomem *irqbase) 157{ 158 struct device_node *np; 159 int irq_base; 160 int i; 161 162 avic_base = irqbase; 163 164 /* put the AVIC into the reset value with 165 * all interrupts disabled 166 */ 167 __raw_writel(0, avic_base + AVIC_INTCNTL); 168 __raw_writel(0x1f, avic_base + AVIC_NIMASK); 169 170 /* disable all interrupts */ 171 __raw_writel(0, avic_base + AVIC_INTENABLEH); 172 __raw_writel(0, avic_base + AVIC_INTENABLEL); 173 174 /* all IRQ no FIQ */ 175 __raw_writel(0, avic_base + AVIC_INTTYPEH); 176 __raw_writel(0, avic_base + AVIC_INTTYPEL); 177 178 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); 179 WARN_ON(irq_base < 0); 180 181 np = of_find_compatible_node(NULL, NULL, "fsl,avic"); 182 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, 183 &irq_domain_simple_ops, NULL); 184 WARN_ON(!domain); 185 186 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) 187 avic_init_gc(i, irq_base); 188 189 /* Set default priority value (0) for all IRQ's */ 190 for (i = 0; i < 8; i++) 191 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); 192 193 set_handle_irq(avic_handle_irq); 194 195#ifdef CONFIG_FIQ 196 /* Initialize FIQ */ 197 init_FIQ(FIQ_START); 198#endif 199 200 printk(KERN_INFO "MXC IRQ initialized\n"); 201} 202