1/*
2 * arch/arm/mach-ks8695/time.c
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20 */
21
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/io.h>
28#include <linux/clockchips.h>
29
30#include <asm/mach/time.h>
31#include <asm/system_misc.h>
32
33#include <mach/regs-irq.h>
34
35#include "generic.h"
36
37#define KS8695_TMR_OFFSET	(0xF0000 + 0xE400)
38#define KS8695_TMR_VA		(KS8695_IO_VA + KS8695_TMR_OFFSET)
39#define KS8695_TMR_PA		(KS8695_IO_PA + KS8695_TMR_OFFSET)
40
41/*
42 * Timer registers
43 */
44#define KS8695_TMCON		(0x00)		/* Timer Control Register */
45#define KS8695_T1TC		(0x04)		/* Timer 1 Timeout Count Register */
46#define KS8695_T0TC		(0x08)		/* Timer 0 Timeout Count Register */
47#define KS8695_T1PD		(0x0C)		/* Timer 1 Pulse Count Register */
48#define KS8695_T0PD		(0x10)		/* Timer 0 Pulse Count Register */
49
50/* Timer Control Register */
51#define TMCON_T1EN		(1 << 1)	/* Timer 1 Enable */
52#define TMCON_T0EN		(1 << 0)	/* Timer 0 Enable */
53
54/* Timer0 Timeout Counter Register */
55#define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */
56
57static void ks8695_set_mode(enum clock_event_mode mode,
58			    struct clock_event_device *evt)
59{
60	u32 tmcon;
61
62	if (mode == CLOCK_EVT_FEAT_PERIODIC) {
63		u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
64		u32 half = DIV_ROUND_CLOSEST(rate, 2);
65
66		/* Disable timer 1 */
67		tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
68		tmcon &= ~TMCON_T1EN;
69		writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
70
71		/* Both registers need to count down */
72		writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
73		writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
74
75		/* Re-enable timer1 */
76		tmcon |= TMCON_T1EN;
77		writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
78	}
79}
80
81static int ks8695_set_next_event(unsigned long cycles,
82				 struct clock_event_device *evt)
83
84{
85	u32 half = DIV_ROUND_CLOSEST(cycles, 2);
86	u32 tmcon;
87
88	/* Disable timer 1 */
89	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
90	tmcon &= ~TMCON_T1EN;
91	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
92
93	/* Both registers need to count down */
94	writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
95	writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
96
97	/* Re-enable timer1 */
98	tmcon |= TMCON_T1EN;
99	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
100
101	return 0;
102}
103
104static struct clock_event_device clockevent_ks8695 = {
105	.name		= "ks8695_t1tc",
106	.rating		= 300, /* Reasonably fast and accurate clock event */
107	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
108	.set_next_event	= ks8695_set_next_event,
109	.set_mode	= ks8695_set_mode,
110};
111
112/*
113 * IRQ handler for the timer.
114 */
115static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
116{
117	struct clock_event_device *evt = &clockevent_ks8695;
118
119	evt->event_handler(evt);
120	return IRQ_HANDLED;
121}
122
123static struct irqaction ks8695_timer_irq = {
124	.name		= "ks8695_tick",
125	.flags		= IRQF_TIMER,
126	.handler	= ks8695_timer_interrupt,
127};
128
129static void ks8695_timer_setup(void)
130{
131	unsigned long tmcon;
132
133	/* Disable timer 0 and 1 */
134	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
135	tmcon &= ~TMCON_T0EN;
136	tmcon &= ~TMCON_T1EN;
137	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
138
139	/*
140	 * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
141	 * (one on each counter) maximum 2*2^32, but the API will only
142	 * accept up to a 32bit full word (0xFFFFFFFFU).
143	 */
144	clockevents_config_and_register(&clockevent_ks8695,
145					KS8695_CLOCK_RATE, 2,
146					0xFFFFFFFFU);
147}
148
149void __init ks8695_timer_init(void)
150{
151	ks8695_timer_setup();
152
153	/* Enable timer interrupts */
154	setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
155}
156
157void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
158{
159	unsigned int reg;
160
161	if (reboot_mode == REBOOT_SOFT)
162		soft_restart(0);
163
164	/* disable timer0 */
165	reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
166	writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
167
168	/* enable watchdog mode */
169	writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
170
171	/* re-enable timer0 */
172	writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
173}
174