1/*
2 *  arch/arm/mach-sti/platsmp.c
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 *		http://www.st.com
6 *
7 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 *
9 *  Copyright (C) 2002 ARM Ltd.
10 *  All Rights Reserved
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/delay.h>
19#include <linux/smp.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23
24#include <asm/cacheflush.h>
25#include <asm/smp_plat.h>
26#include <asm/smp_scu.h>
27
28#include "smp.h"
29
30static void write_pen_release(int val)
31{
32	pen_release = val;
33	smp_wmb();
34	sync_cache_w(&pen_release);
35}
36
37static DEFINE_SPINLOCK(boot_lock);
38
39static void sti_secondary_init(unsigned int cpu)
40{
41	trace_hardirqs_off();
42
43	/*
44	 * let the primary processor know we're out of the
45	 * pen, then head off into the C entry point
46	 */
47	write_pen_release(-1);
48
49	/*
50	 * Synchronise with the boot thread.
51	 */
52	spin_lock(&boot_lock);
53	spin_unlock(&boot_lock);
54}
55
56static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
57{
58	unsigned long timeout;
59
60	/*
61	 * set synchronisation state between this boot processor
62	 * and the secondary one
63	 */
64	spin_lock(&boot_lock);
65
66	/*
67	 * The secondary processor is waiting to be released from
68	 * the holding pen - release it, then wait for it to flag
69	 * that it has been released by resetting pen_release.
70	 *
71	 * Note that "pen_release" is the hardware CPU ID, whereas
72	 * "cpu" is Linux's internal ID.
73	 */
74	write_pen_release(cpu_logical_map(cpu));
75
76	/*
77	 * Send the secondary CPU a soft interrupt, thereby causing
78	 * it to jump to the secondary entrypoint.
79	 */
80	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
81
82	timeout = jiffies + (1 * HZ);
83	while (time_before(jiffies, timeout)) {
84		smp_rmb();
85		if (pen_release == -1)
86			break;
87
88		udelay(10);
89	}
90
91	/*
92	 * now the secondary core is starting up let it run its
93	 * calibrations, then wait for it to finish
94	 */
95	spin_unlock(&boot_lock);
96
97	return pen_release != -1 ? -ENOSYS : 0;
98}
99
100static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
101{
102	void __iomem *scu_base = NULL;
103	struct device_node *np = of_find_compatible_node(
104					NULL, NULL, "arm,cortex-a9-scu");
105	if (np) {
106		scu_base = of_iomap(np, 0);
107		scu_enable(scu_base);
108		of_node_put(np);
109	}
110}
111
112struct smp_operations __initdata sti_smp_ops = {
113	.smp_prepare_cpus	= sti_smp_prepare_cpus,
114	.smp_secondary_init	= sti_secondary_init,
115	.smp_boot_secondary	= sti_boot_secondary,
116};
117