1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_CPUTYPE_H
17#define __ASM_CPUTYPE_H
18
19#define INVALID_HWID		ULONG_MAX
20
21#define MPIDR_UP_BITMASK	(0x1 << 30)
22#define MPIDR_MT_BITMASK	(0x1 << 24)
23#define MPIDR_HWID_BITMASK	0xff00ffffff
24
25#define MPIDR_LEVEL_BITS_SHIFT	3
26#define MPIDR_LEVEL_BITS	(1 << MPIDR_LEVEL_BITS_SHIFT)
27#define MPIDR_LEVEL_MASK	((1 << MPIDR_LEVEL_BITS) - 1)
28
29#define MPIDR_LEVEL_SHIFT(level) \
30	(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
31
32#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
33	((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
34
35#define read_cpuid(reg) ({						\
36	u64 __val;							\
37	asm("mrs	%0, " #reg : "=r" (__val));			\
38	__val;								\
39})
40
41#define MIDR_REVISION_MASK	0xf
42#define MIDR_REVISION(midr)	((midr) & MIDR_REVISION_MASK)
43#define MIDR_PARTNUM_SHIFT	4
44#define MIDR_PARTNUM_MASK	(0xfff << MIDR_PARTNUM_SHIFT)
45#define MIDR_PARTNUM(midr)	\
46	(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
47#define MIDR_ARCHITECTURE_SHIFT	16
48#define MIDR_ARCHITECTURE_MASK	(0xf << MIDR_ARCHITECTURE_SHIFT)
49#define MIDR_ARCHITECTURE(midr)	\
50	(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
51#define MIDR_VARIANT_SHIFT	20
52#define MIDR_VARIANT_MASK	(0xf << MIDR_VARIANT_SHIFT)
53#define MIDR_VARIANT(midr)	\
54	(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
55#define MIDR_IMPLEMENTOR_SHIFT	24
56#define MIDR_IMPLEMENTOR_MASK	(0xff << MIDR_IMPLEMENTOR_SHIFT)
57#define MIDR_IMPLEMENTOR(midr)	\
58	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
59
60#define MIDR_CPU_PART(imp, partnum) \
61	(((imp)			<< MIDR_IMPLEMENTOR_SHIFT) | \
62	(0xf			<< MIDR_ARCHITECTURE_SHIFT) | \
63	((partnum)		<< MIDR_PARTNUM_SHIFT))
64
65#define ARM_CPU_IMP_ARM		0x41
66#define ARM_CPU_IMP_APM		0x50
67
68#define ARM_CPU_PART_AEM_V8	0xD0F
69#define ARM_CPU_PART_FOUNDATION	0xD00
70#define ARM_CPU_PART_CORTEX_A57	0xD07
71#define ARM_CPU_PART_CORTEX_A53	0xD03
72
73#define APM_CPU_PART_POTENZA	0x000
74
75#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16
76#define ID_AA64MMFR0_BIGENDEL0_MASK	(0xf << ID_AA64MMFR0_BIGENDEL0_SHIFT)
77#define ID_AA64MMFR0_BIGENDEL0(mmfr0)	\
78	(((mmfr0) & ID_AA64MMFR0_BIGENDEL0_MASK) >> ID_AA64MMFR0_BIGENDEL0_SHIFT)
79#define ID_AA64MMFR0_BIGEND_SHIFT	8
80#define ID_AA64MMFR0_BIGEND_MASK	(0xf << ID_AA64MMFR0_BIGEND_SHIFT)
81#define ID_AA64MMFR0_BIGEND(mmfr0)	\
82	(((mmfr0) & ID_AA64MMFR0_BIGEND_MASK) >> ID_AA64MMFR0_BIGEND_SHIFT)
83
84#define SCTLR_EL1_CP15BEN	(0x1 << 5)
85#define SCTLR_EL1_SED		(0x1 << 8)
86
87#ifndef __ASSEMBLY__
88
89/*
90 * The CPU ID never changes at run time, so we might as well tell the
91 * compiler that it's constant.  Use this function to read the CPU ID
92 * rather than directly reading processor_id or read_cpuid() directly.
93 */
94static inline u32 __attribute_const__ read_cpuid_id(void)
95{
96	return read_cpuid(MIDR_EL1);
97}
98
99static inline u64 __attribute_const__ read_cpuid_mpidr(void)
100{
101	return read_cpuid(MPIDR_EL1);
102}
103
104static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
105{
106	return MIDR_IMPLEMENTOR(read_cpuid_id());
107}
108
109static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
110{
111	return MIDR_PARTNUM(read_cpuid_id());
112}
113
114static inline u32 __attribute_const__ read_cpuid_cachetype(void)
115{
116	return read_cpuid(CTR_EL0);
117}
118
119static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
120{
121	return (ID_AA64MMFR0_BIGEND(mmfr0) == 0x1) ||
122		(ID_AA64MMFR0_BIGENDEL0(mmfr0) == 0x1);
123}
124#endif /* __ASSEMBLY__ */
125
126#endif
127