1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_HW_BREAKPOINT_H
17#define __ASM_HW_BREAKPOINT_H
18
19#ifdef __KERNEL__
20
21struct arch_hw_breakpoint_ctrl {
22	u32 __reserved	: 19,
23	len		: 8,
24	type		: 2,
25	privilege	: 2,
26	enabled		: 1;
27};
28
29struct arch_hw_breakpoint {
30	u64 address;
31	u64 trigger;
32	struct arch_hw_breakpoint_ctrl ctrl;
33};
34
35static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
36{
37	return (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
38		ctrl.enabled;
39}
40
41static inline void decode_ctrl_reg(u32 reg,
42				   struct arch_hw_breakpoint_ctrl *ctrl)
43{
44	ctrl->enabled	= reg & 0x1;
45	reg >>= 1;
46	ctrl->privilege	= reg & 0x3;
47	reg >>= 2;
48	ctrl->type	= reg & 0x3;
49	reg >>= 2;
50	ctrl->len	= reg & 0xff;
51}
52
53/* Breakpoint */
54#define ARM_BREAKPOINT_EXECUTE	0
55
56/* Watchpoints */
57#define ARM_BREAKPOINT_LOAD	1
58#define ARM_BREAKPOINT_STORE	2
59#define AARCH64_ESR_ACCESS_MASK	(1 << 6)
60
61/* Privilege Levels */
62#define AARCH64_BREAKPOINT_EL1	1
63#define AARCH64_BREAKPOINT_EL0	2
64
65/* Lengths */
66#define ARM_BREAKPOINT_LEN_1	0x1
67#define ARM_BREAKPOINT_LEN_2	0x3
68#define ARM_BREAKPOINT_LEN_4	0xf
69#define ARM_BREAKPOINT_LEN_8	0xff
70
71/* Kernel stepping */
72#define ARM_KERNEL_STEP_NONE	0
73#define ARM_KERNEL_STEP_ACTIVE	1
74#define ARM_KERNEL_STEP_SUSPEND	2
75
76/*
77 * Limits.
78 * Changing these will require modifications to the register accessors.
79 */
80#define ARM_MAX_BRP		16
81#define ARM_MAX_WRP		16
82
83/* Virtual debug register bases. */
84#define AARCH64_DBG_REG_BVR	0
85#define AARCH64_DBG_REG_BCR	(AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
86#define AARCH64_DBG_REG_WVR	(AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
87#define AARCH64_DBG_REG_WCR	(AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
88
89/* Debug register names. */
90#define AARCH64_DBG_REG_NAME_BVR	"bvr"
91#define AARCH64_DBG_REG_NAME_BCR	"bcr"
92#define AARCH64_DBG_REG_NAME_WVR	"wvr"
93#define AARCH64_DBG_REG_NAME_WCR	"wcr"
94
95/* Accessor macros for the debug registers. */
96#define AARCH64_DBG_READ(N, REG, VAL) do {\
97	asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\
98} while (0)
99
100#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
101	asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
102} while (0)
103
104struct task_struct;
105struct notifier_block;
106struct perf_event;
107struct pmu;
108
109extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
110				  int *gen_len, int *gen_type);
111extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
112extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
113extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
114					   unsigned long val, void *data);
115
116extern int arch_install_hw_breakpoint(struct perf_event *bp);
117extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
118extern void hw_breakpoint_pmu_read(struct perf_event *bp);
119extern int hw_breakpoint_slots(int type);
120
121#ifdef CONFIG_HAVE_HW_BREAKPOINT
122extern void hw_breakpoint_thread_switch(struct task_struct *next);
123extern void ptrace_hw_copy_thread(struct task_struct *task);
124#else
125static inline void hw_breakpoint_thread_switch(struct task_struct *next)
126{
127}
128static inline void ptrace_hw_copy_thread(struct task_struct *task)
129{
130}
131#endif
132
133extern struct pmu perf_ops_bp;
134
135#endif	/* __KERNEL__ */
136#endif	/* __ASM_BREAKPOINT_H */
137