1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ARM64_KVM_ARM_H__
19#define __ARM64_KVM_ARM_H__
20
21#include <asm/esr.h>
22#include <asm/memory.h>
23#include <asm/types.h>
24
25/* Hyp Configuration Register (HCR) bits */
26#define HCR_ID		(UL(1) << 33)
27#define HCR_CD		(UL(1) << 32)
28#define HCR_RW_SHIFT	31
29#define HCR_RW		(UL(1) << HCR_RW_SHIFT)
30#define HCR_TRVM	(UL(1) << 30)
31#define HCR_HCD		(UL(1) << 29)
32#define HCR_TDZ		(UL(1) << 28)
33#define HCR_TGE		(UL(1) << 27)
34#define HCR_TVM		(UL(1) << 26)
35#define HCR_TTLB	(UL(1) << 25)
36#define HCR_TPU		(UL(1) << 24)
37#define HCR_TPC		(UL(1) << 23)
38#define HCR_TSW		(UL(1) << 22)
39#define HCR_TAC		(UL(1) << 21)
40#define HCR_TIDCP	(UL(1) << 20)
41#define HCR_TSC		(UL(1) << 19)
42#define HCR_TID3	(UL(1) << 18)
43#define HCR_TID2	(UL(1) << 17)
44#define HCR_TID1	(UL(1) << 16)
45#define HCR_TID0	(UL(1) << 15)
46#define HCR_TWE		(UL(1) << 14)
47#define HCR_TWI		(UL(1) << 13)
48#define HCR_DC		(UL(1) << 12)
49#define HCR_BSU		(3 << 10)
50#define HCR_BSU_IS	(UL(1) << 10)
51#define HCR_FB		(UL(1) << 9)
52#define HCR_VA		(UL(1) << 8)
53#define HCR_VI		(UL(1) << 7)
54#define HCR_VF		(UL(1) << 6)
55#define HCR_AMO		(UL(1) << 5)
56#define HCR_IMO		(UL(1) << 4)
57#define HCR_FMO		(UL(1) << 3)
58#define HCR_PTW		(UL(1) << 2)
59#define HCR_SWIO	(UL(1) << 1)
60#define HCR_VM		(UL(1) << 0)
61
62/*
63 * The bits we set in HCR:
64 * RW:		64bit by default, can be overriden for 32bit VMs
65 * TAC:		Trap ACTLR
66 * TSC:		Trap SMC
67 * TVM:		Trap VM ops (until M+C set in SCTLR_EL1)
68 * TSW:		Trap cache operations by set/way
69 * TWE:		Trap WFE
70 * TWI:		Trap WFI
71 * TIDCP:	Trap L2CTLR/L2ECTLR
72 * BSU_IS:	Upgrade barriers to the inner shareable domain
73 * FB:		Force broadcast of all maintainance operations
74 * AMO:		Override CPSR.A and enable signaling with VA
75 * IMO:		Override CPSR.I and enable signaling with VI
76 * FMO:		Override CPSR.F and enable signaling with VF
77 * SWIO:	Turn set/way invalidates into set/way clean+invalidate
78 */
79#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
80			 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
81			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW)
82#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
83#define HCR_INT_OVERRIDE   (HCR_FMO | HCR_IMO)
84
85
86/* Hyp System Control Register (SCTLR_EL2) bits */
87#define SCTLR_EL2_EE	(1 << 25)
88#define SCTLR_EL2_WXN	(1 << 19)
89#define SCTLR_EL2_I	(1 << 12)
90#define SCTLR_EL2_SA	(1 << 3)
91#define SCTLR_EL2_C	(1 << 2)
92#define SCTLR_EL2_A	(1 << 1)
93#define SCTLR_EL2_M	1
94#define SCTLR_EL2_FLAGS	(SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C |	\
95			 SCTLR_EL2_SA | SCTLR_EL2_I)
96
97/* TCR_EL2 Registers bits */
98#define TCR_EL2_TBI	(1 << 20)
99#define TCR_EL2_PS	(7 << 16)
100#define TCR_EL2_PS_40B	(2 << 16)
101#define TCR_EL2_TG0	(1 << 14)
102#define TCR_EL2_SH0	(3 << 12)
103#define TCR_EL2_ORGN0	(3 << 10)
104#define TCR_EL2_IRGN0	(3 << 8)
105#define TCR_EL2_T0SZ	0x3f
106#define TCR_EL2_MASK	(TCR_EL2_TG0 | TCR_EL2_SH0 | \
107			 TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)
108
109#define TCR_EL2_FLAGS	(TCR_EL2_PS_40B)
110
111/* VTCR_EL2 Registers bits */
112#define VTCR_EL2_PS_MASK	(7 << 16)
113#define VTCR_EL2_TG0_MASK	(1 << 14)
114#define VTCR_EL2_TG0_4K		(0 << 14)
115#define VTCR_EL2_TG0_64K	(1 << 14)
116#define VTCR_EL2_SH0_MASK	(3 << 12)
117#define VTCR_EL2_SH0_INNER	(3 << 12)
118#define VTCR_EL2_ORGN0_MASK	(3 << 10)
119#define VTCR_EL2_ORGN0_WBWA	(1 << 10)
120#define VTCR_EL2_IRGN0_MASK	(3 << 8)
121#define VTCR_EL2_IRGN0_WBWA	(1 << 8)
122#define VTCR_EL2_SL0_MASK	(3 << 6)
123#define VTCR_EL2_SL0_LVL1	(1 << 6)
124#define VTCR_EL2_T0SZ_MASK	0x3f
125#define VTCR_EL2_T0SZ_40B	24
126
127/*
128 * We configure the Stage-2 page tables to always restrict the IPA space to be
129 * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
130 * not known to exist and will break with this configuration.
131 *
132 * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
133 * (see hyp-init.S).
134 *
135 * Note that when using 4K pages, we concatenate two first level page tables
136 * together.
137 *
138 * The magic numbers used for VTTBR_X in this patch can be found in Tables
139 * D4-23 and D4-25 in ARM DDI 0487A.b.
140 */
141#ifdef CONFIG_ARM64_64K_PAGES
142/*
143 * Stage2 translation configuration:
144 * 40bits input  (T0SZ = 24)
145 * 64kB pages (TG0 = 1)
146 * 2 level page tables (SL = 1)
147 */
148#define VTCR_EL2_FLAGS		(VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \
149				 VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
150				 VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
151#define VTTBR_X		(38 - VTCR_EL2_T0SZ_40B)
152#else
153/*
154 * Stage2 translation configuration:
155 * 40bits input  (T0SZ = 24)
156 * 4kB pages (TG0 = 0)
157 * 3 level page tables (SL = 1)
158 */
159#define VTCR_EL2_FLAGS		(VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \
160				 VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
161				 VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
162#define VTTBR_X		(37 - VTCR_EL2_T0SZ_40B)
163#endif
164
165#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
166#define VTTBR_BADDR_MASK  (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
167#define VTTBR_VMID_SHIFT  (UL(48))
168#define VTTBR_VMID_MASK	  (UL(0xFF) << VTTBR_VMID_SHIFT)
169
170/* Hyp System Trap Register */
171#define HSTR_EL2_TTEE	(1 << 16)
172#define HSTR_EL2_T(x)	(1 << x)
173
174/* Hyp Coprocessor Trap Register */
175#define CPTR_EL2_TCPAC	(1 << 31)
176#define CPTR_EL2_TTA	(1 << 20)
177#define CPTR_EL2_TFP	(1 << 10)
178
179/* Hyp Debug Configuration Register bits */
180#define MDCR_EL2_TDRA		(1 << 11)
181#define MDCR_EL2_TDOSA		(1 << 10)
182#define MDCR_EL2_TDA		(1 << 9)
183#define MDCR_EL2_TDE		(1 << 8)
184#define MDCR_EL2_HPME		(1 << 7)
185#define MDCR_EL2_TPM		(1 << 6)
186#define MDCR_EL2_TPMCR		(1 << 5)
187#define MDCR_EL2_HPMN_MASK	(0x1F)
188
189/* For compatibility with fault code shared with 32-bit */
190#define FSC_FAULT	ESR_ELx_FSC_FAULT
191#define FSC_ACCESS	ESR_ELx_FSC_ACCESS
192#define FSC_PERM	ESR_ELx_FSC_PERM
193
194/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
195#define HPFAR_MASK	(~UL(0xf))
196
197#endif /* __ARM64_KVM_ARM_H__ */
198