1/* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8#include <linux/clk.h> 9#include <linux/delay.h> 10#include <linux/platform_data/dma-dw.h> 11#include <linux/fb.h> 12#include <linux/init.h> 13#include <linux/platform_device.h> 14#include <linux/dma-mapping.h> 15#include <linux/slab.h> 16#include <linux/gpio.h> 17#include <linux/spi/spi.h> 18#include <linux/usb/atmel_usba_udc.h> 19 20#include <linux/platform_data/mmc-atmel-mci.h> 21#include <linux/atmel-mci.h> 22 23#include <asm/io.h> 24#include <asm/irq.h> 25 26#include <mach/at32ap700x.h> 27#include <mach/board.h> 28#include <mach/hmatrix.h> 29#include <mach/portmux.h> 30#include <mach/sram.h> 31 32#include <sound/atmel-abdac.h> 33#include <sound/atmel-ac97c.h> 34 35#include <video/atmel_lcdc.h> 36 37#include "clock.h" 38#include "pio.h" 39#include "pm.h" 40 41 42#define PBMEM(base) \ 43 { \ 44 .start = base, \ 45 .end = base + 0x3ff, \ 46 .flags = IORESOURCE_MEM, \ 47 } 48#define IRQ(num) \ 49 { \ 50 .start = num, \ 51 .end = num, \ 52 .flags = IORESOURCE_IRQ, \ 53 } 54#define NAMED_IRQ(num, _name) \ 55 { \ 56 .start = num, \ 57 .end = num, \ 58 .name = _name, \ 59 .flags = IORESOURCE_IRQ, \ 60 } 61 62/* REVISIT these assume *every* device supports DMA, but several 63 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more. 64 */ 65#define DEFINE_DEV(_name, _id) \ 66static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \ 67static struct platform_device _name##_id##_device = { \ 68 .name = #_name, \ 69 .id = _id, \ 70 .dev = { \ 71 .dma_mask = &_name##_id##_dma_mask, \ 72 .coherent_dma_mask = DMA_BIT_MASK(32), \ 73 }, \ 74 .resource = _name##_id##_resource, \ 75 .num_resources = ARRAY_SIZE(_name##_id##_resource), \ 76} 77#define DEFINE_DEV_DATA(_name, _id) \ 78static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \ 79static struct platform_device _name##_id##_device = { \ 80 .name = #_name, \ 81 .id = _id, \ 82 .dev = { \ 83 .dma_mask = &_name##_id##_dma_mask, \ 84 .platform_data = &_name##_id##_data, \ 85 .coherent_dma_mask = DMA_BIT_MASK(32), \ 86 }, \ 87 .resource = _name##_id##_resource, \ 88 .num_resources = ARRAY_SIZE(_name##_id##_resource), \ 89} 90 91#define select_peripheral(port, pin_mask, periph, flags) \ 92 at32_select_periph(GPIO_##port##_BASE, pin_mask, \ 93 GPIO_##periph, flags) 94 95#define DEV_CLK(_name, devname, bus, _index) \ 96static struct clk devname##_##_name = { \ 97 .name = #_name, \ 98 .dev = &devname##_device.dev, \ 99 .parent = &bus##_clk, \ 100 .mode = bus##_clk_mode, \ 101 .get_rate = bus##_clk_get_rate, \ 102 .index = _index, \ 103} 104 105static DEFINE_SPINLOCK(pm_lock); 106 107static struct clk osc0; 108static struct clk osc1; 109 110static unsigned long osc_get_rate(struct clk *clk) 111{ 112 return at32_board_osc_rates[clk->index]; 113} 114 115static unsigned long pll_get_rate(struct clk *clk, unsigned long control) 116{ 117 unsigned long div, mul, rate; 118 119 div = PM_BFEXT(PLLDIV, control) + 1; 120 mul = PM_BFEXT(PLLMUL, control) + 1; 121 122 rate = clk->parent->get_rate(clk->parent); 123 rate = (rate + div / 2) / div; 124 rate *= mul; 125 126 return rate; 127} 128 129static long pll_set_rate(struct clk *clk, unsigned long rate, 130 u32 *pll_ctrl) 131{ 132 unsigned long mul; 133 unsigned long mul_best_fit = 0; 134 unsigned long div; 135 unsigned long div_min; 136 unsigned long div_max; 137 unsigned long div_best_fit = 0; 138 unsigned long base; 139 unsigned long pll_in; 140 unsigned long actual = 0; 141 unsigned long rate_error; 142 unsigned long rate_error_prev = ~0UL; 143 u32 ctrl; 144 145 /* Rate must be between 80 MHz and 200 Mhz. */ 146 if (rate < 80000000UL || rate > 200000000UL) 147 return -EINVAL; 148 149 ctrl = PM_BF(PLLOPT, 4); 150 base = clk->parent->get_rate(clk->parent); 151 152 /* PLL input frequency must be between 6 MHz and 32 MHz. */ 153 div_min = DIV_ROUND_UP(base, 32000000UL); 154 div_max = base / 6000000UL; 155 156 if (div_max < div_min) 157 return -EINVAL; 158 159 for (div = div_min; div <= div_max; div++) { 160 pll_in = (base + div / 2) / div; 161 mul = (rate + pll_in / 2) / pll_in; 162 163 if (mul == 0) 164 continue; 165 166 actual = pll_in * mul; 167 rate_error = abs(actual - rate); 168 169 if (rate_error < rate_error_prev) { 170 mul_best_fit = mul; 171 div_best_fit = div; 172 rate_error_prev = rate_error; 173 } 174 175 if (rate_error == 0) 176 break; 177 } 178 179 if (div_best_fit == 0) 180 return -EINVAL; 181 182 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1); 183 ctrl |= PM_BF(PLLDIV, div_best_fit - 1); 184 ctrl |= PM_BF(PLLCOUNT, 16); 185 186 if (clk->parent == &osc1) 187 ctrl |= PM_BIT(PLLOSC); 188 189 *pll_ctrl = ctrl; 190 191 return actual; 192} 193 194static unsigned long pll0_get_rate(struct clk *clk) 195{ 196 u32 control; 197 198 control = pm_readl(PLL0); 199 200 return pll_get_rate(clk, control); 201} 202 203static void pll1_mode(struct clk *clk, int enabled) 204{ 205 unsigned long timeout; 206 u32 status; 207 u32 ctrl; 208 209 ctrl = pm_readl(PLL1); 210 211 if (enabled) { 212 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) { 213 pr_debug("clk %s: failed to enable, rate not set\n", 214 clk->name); 215 return; 216 } 217 218 ctrl |= PM_BIT(PLLEN); 219 pm_writel(PLL1, ctrl); 220 221 /* Wait for PLL lock. */ 222 for (timeout = 10000; timeout; timeout--) { 223 status = pm_readl(ISR); 224 if (status & PM_BIT(LOCK1)) 225 break; 226 udelay(10); 227 } 228 229 if (!(status & PM_BIT(LOCK1))) 230 printk(KERN_ERR "clk %s: timeout waiting for lock\n", 231 clk->name); 232 } else { 233 ctrl &= ~PM_BIT(PLLEN); 234 pm_writel(PLL1, ctrl); 235 } 236} 237 238static unsigned long pll1_get_rate(struct clk *clk) 239{ 240 u32 control; 241 242 control = pm_readl(PLL1); 243 244 return pll_get_rate(clk, control); 245} 246 247static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply) 248{ 249 u32 ctrl = 0; 250 unsigned long actual_rate; 251 252 actual_rate = pll_set_rate(clk, rate, &ctrl); 253 254 if (apply) { 255 if (actual_rate != rate) 256 return -EINVAL; 257 if (clk->users > 0) 258 return -EBUSY; 259 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n", 260 clk->name, rate, actual_rate); 261 pm_writel(PLL1, ctrl); 262 } 263 264 return actual_rate; 265} 266 267static int pll1_set_parent(struct clk *clk, struct clk *parent) 268{ 269 u32 ctrl; 270 271 if (clk->users > 0) 272 return -EBUSY; 273 274 ctrl = pm_readl(PLL1); 275 WARN_ON(ctrl & PM_BIT(PLLEN)); 276 277 if (parent == &osc0) 278 ctrl &= ~PM_BIT(PLLOSC); 279 else if (parent == &osc1) 280 ctrl |= PM_BIT(PLLOSC); 281 else 282 return -EINVAL; 283 284 pm_writel(PLL1, ctrl); 285 clk->parent = parent; 286 287 return 0; 288} 289 290/* 291 * The AT32AP7000 has five primary clock sources: One 32kHz 292 * oscillator, two crystal oscillators and two PLLs. 293 */ 294static struct clk osc32k = { 295 .name = "osc32k", 296 .get_rate = osc_get_rate, 297 .users = 1, 298 .index = 0, 299}; 300static struct clk osc0 = { 301 .name = "osc0", 302 .get_rate = osc_get_rate, 303 .users = 1, 304 .index = 1, 305}; 306static struct clk osc1 = { 307 .name = "osc1", 308 .get_rate = osc_get_rate, 309 .index = 2, 310}; 311static struct clk pll0 = { 312 .name = "pll0", 313 .get_rate = pll0_get_rate, 314 .parent = &osc0, 315}; 316static struct clk pll1 = { 317 .name = "pll1", 318 .mode = pll1_mode, 319 .get_rate = pll1_get_rate, 320 .set_rate = pll1_set_rate, 321 .set_parent = pll1_set_parent, 322 .parent = &osc0, 323}; 324 325/* 326 * The main clock can be either osc0 or pll0. The boot loader may 327 * have chosen one for us, so we don't really know which one until we 328 * have a look at the SM. 329 */ 330static struct clk *main_clock; 331 332/* 333 * Synchronous clocks are generated from the main clock. The clocks 334 * must satisfy the constraint 335 * fCPU >= fHSB >= fPB 336 * i.e. each clock must not be faster than its parent. 337 */ 338static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) 339{ 340 return main_clock->get_rate(main_clock) >> shift; 341}; 342 343static void cpu_clk_mode(struct clk *clk, int enabled) 344{ 345 unsigned long flags; 346 u32 mask; 347 348 spin_lock_irqsave(&pm_lock, flags); 349 mask = pm_readl(CPU_MASK); 350 if (enabled) 351 mask |= 1 << clk->index; 352 else 353 mask &= ~(1 << clk->index); 354 pm_writel(CPU_MASK, mask); 355 spin_unlock_irqrestore(&pm_lock, flags); 356} 357 358static unsigned long cpu_clk_get_rate(struct clk *clk) 359{ 360 unsigned long cksel, shift = 0; 361 362 cksel = pm_readl(CKSEL); 363 if (cksel & PM_BIT(CPUDIV)) 364 shift = PM_BFEXT(CPUSEL, cksel) + 1; 365 366 return bus_clk_get_rate(clk, shift); 367} 368 369static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply) 370{ 371 u32 control; 372 unsigned long parent_rate, child_div, actual_rate, div; 373 374 parent_rate = clk->parent->get_rate(clk->parent); 375 control = pm_readl(CKSEL); 376 377 if (control & PM_BIT(HSBDIV)) 378 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1); 379 else 380 child_div = 1; 381 382 if (rate > 3 * (parent_rate / 4) || child_div == 1) { 383 actual_rate = parent_rate; 384 control &= ~PM_BIT(CPUDIV); 385 } else { 386 unsigned int cpusel; 387 div = (parent_rate + rate / 2) / rate; 388 if (div > child_div) 389 div = child_div; 390 cpusel = (div > 1) ? (fls(div) - 2) : 0; 391 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control); 392 actual_rate = parent_rate / (1 << (cpusel + 1)); 393 } 394 395 pr_debug("clk %s: new rate %lu (actual rate %lu)\n", 396 clk->name, rate, actual_rate); 397 398 if (apply) 399 pm_writel(CKSEL, control); 400 401 return actual_rate; 402} 403 404static void hsb_clk_mode(struct clk *clk, int enabled) 405{ 406 unsigned long flags; 407 u32 mask; 408 409 spin_lock_irqsave(&pm_lock, flags); 410 mask = pm_readl(HSB_MASK); 411 if (enabled) 412 mask |= 1 << clk->index; 413 else 414 mask &= ~(1 << clk->index); 415 pm_writel(HSB_MASK, mask); 416 spin_unlock_irqrestore(&pm_lock, flags); 417} 418 419static unsigned long hsb_clk_get_rate(struct clk *clk) 420{ 421 unsigned long cksel, shift = 0; 422 423 cksel = pm_readl(CKSEL); 424 if (cksel & PM_BIT(HSBDIV)) 425 shift = PM_BFEXT(HSBSEL, cksel) + 1; 426 427 return bus_clk_get_rate(clk, shift); 428} 429 430void pba_clk_mode(struct clk *clk, int enabled) 431{ 432 unsigned long flags; 433 u32 mask; 434 435 spin_lock_irqsave(&pm_lock, flags); 436 mask = pm_readl(PBA_MASK); 437 if (enabled) 438 mask |= 1 << clk->index; 439 else 440 mask &= ~(1 << clk->index); 441 pm_writel(PBA_MASK, mask); 442 spin_unlock_irqrestore(&pm_lock, flags); 443} 444 445unsigned long pba_clk_get_rate(struct clk *clk) 446{ 447 unsigned long cksel, shift = 0; 448 449 cksel = pm_readl(CKSEL); 450 if (cksel & PM_BIT(PBADIV)) 451 shift = PM_BFEXT(PBASEL, cksel) + 1; 452 453 return bus_clk_get_rate(clk, shift); 454} 455 456static void pbb_clk_mode(struct clk *clk, int enabled) 457{ 458 unsigned long flags; 459 u32 mask; 460 461 spin_lock_irqsave(&pm_lock, flags); 462 mask = pm_readl(PBB_MASK); 463 if (enabled) 464 mask |= 1 << clk->index; 465 else 466 mask &= ~(1 << clk->index); 467 pm_writel(PBB_MASK, mask); 468 spin_unlock_irqrestore(&pm_lock, flags); 469} 470 471static unsigned long pbb_clk_get_rate(struct clk *clk) 472{ 473 unsigned long cksel, shift = 0; 474 475 cksel = pm_readl(CKSEL); 476 if (cksel & PM_BIT(PBBDIV)) 477 shift = PM_BFEXT(PBBSEL, cksel) + 1; 478 479 return bus_clk_get_rate(clk, shift); 480} 481 482static struct clk cpu_clk = { 483 .name = "cpu", 484 .get_rate = cpu_clk_get_rate, 485 .set_rate = cpu_clk_set_rate, 486 .users = 1, 487}; 488static struct clk hsb_clk = { 489 .name = "hsb", 490 .parent = &cpu_clk, 491 .get_rate = hsb_clk_get_rate, 492}; 493static struct clk pba_clk = { 494 .name = "pba", 495 .parent = &hsb_clk, 496 .mode = hsb_clk_mode, 497 .get_rate = pba_clk_get_rate, 498 .index = 1, 499}; 500static struct clk pbb_clk = { 501 .name = "pbb", 502 .parent = &hsb_clk, 503 .mode = hsb_clk_mode, 504 .get_rate = pbb_clk_get_rate, 505 .users = 1, 506 .index = 2, 507}; 508 509/* -------------------------------------------------------------------- 510 * Generic Clock operations 511 * -------------------------------------------------------------------- */ 512 513static void genclk_mode(struct clk *clk, int enabled) 514{ 515 u32 control; 516 517 control = pm_readl(GCCTRL(clk->index)); 518 if (enabled) 519 control |= PM_BIT(CEN); 520 else 521 control &= ~PM_BIT(CEN); 522 pm_writel(GCCTRL(clk->index), control); 523} 524 525static unsigned long genclk_get_rate(struct clk *clk) 526{ 527 u32 control; 528 unsigned long div = 1; 529 530 control = pm_readl(GCCTRL(clk->index)); 531 if (control & PM_BIT(DIVEN)) 532 div = 2 * (PM_BFEXT(DIV, control) + 1); 533 534 return clk->parent->get_rate(clk->parent) / div; 535} 536 537static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) 538{ 539 u32 control; 540 unsigned long parent_rate, actual_rate, div; 541 542 parent_rate = clk->parent->get_rate(clk->parent); 543 control = pm_readl(GCCTRL(clk->index)); 544 545 if (rate > 3 * parent_rate / 4) { 546 actual_rate = parent_rate; 547 control &= ~PM_BIT(DIVEN); 548 } else { 549 div = (parent_rate + rate) / (2 * rate) - 1; 550 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); 551 actual_rate = parent_rate / (2 * (div + 1)); 552 } 553 554 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n", 555 clk->name, rate, actual_rate); 556 557 if (apply) 558 pm_writel(GCCTRL(clk->index), control); 559 560 return actual_rate; 561} 562 563int genclk_set_parent(struct clk *clk, struct clk *parent) 564{ 565 u32 control; 566 567 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n", 568 clk->name, parent->name, clk->parent->name); 569 570 control = pm_readl(GCCTRL(clk->index)); 571 572 if (parent == &osc1 || parent == &pll1) 573 control |= PM_BIT(OSCSEL); 574 else if (parent == &osc0 || parent == &pll0) 575 control &= ~PM_BIT(OSCSEL); 576 else 577 return -EINVAL; 578 579 if (parent == &pll0 || parent == &pll1) 580 control |= PM_BIT(PLLSEL); 581 else 582 control &= ~PM_BIT(PLLSEL); 583 584 pm_writel(GCCTRL(clk->index), control); 585 clk->parent = parent; 586 587 return 0; 588} 589 590static void __init genclk_init_parent(struct clk *clk) 591{ 592 u32 control; 593 struct clk *parent; 594 595 BUG_ON(clk->index > 7); 596 597 control = pm_readl(GCCTRL(clk->index)); 598 if (control & PM_BIT(OSCSEL)) 599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; 600 else 601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; 602 603 clk->parent = parent; 604} 605 606static struct dw_dma_platform_data dw_dmac0_data = { 607 .nr_channels = 3, 608 .block_size = 4095U, 609 .nr_masters = 2, 610 .data_width = { 2, 2 }, 611}; 612 613static struct resource dw_dmac0_resource[] = { 614 PBMEM(0xff200000), 615 IRQ(2), 616}; 617DEFINE_DEV_DATA(dw_dmac, 0); 618DEV_CLK(hclk, dw_dmac0, hsb, 10); 619 620/* -------------------------------------------------------------------- 621 * System peripherals 622 * -------------------------------------------------------------------- */ 623static struct resource at32_pm0_resource[] = { 624 { 625 .start = 0xfff00000, 626 .end = 0xfff0007f, 627 .flags = IORESOURCE_MEM, 628 }, 629 IRQ(20), 630}; 631 632static struct resource at32ap700x_rtc0_resource[] = { 633 { 634 .start = 0xfff00080, 635 .end = 0xfff000af, 636 .flags = IORESOURCE_MEM, 637 }, 638 IRQ(21), 639}; 640 641static struct resource at32_wdt0_resource[] = { 642 { 643 .start = 0xfff000b0, 644 .end = 0xfff000cf, 645 .flags = IORESOURCE_MEM, 646 }, 647}; 648 649static struct resource at32_eic0_resource[] = { 650 { 651 .start = 0xfff00100, 652 .end = 0xfff0013f, 653 .flags = IORESOURCE_MEM, 654 }, 655 IRQ(19), 656}; 657 658DEFINE_DEV(at32_pm, 0); 659DEFINE_DEV(at32ap700x_rtc, 0); 660DEFINE_DEV(at32_wdt, 0); 661DEFINE_DEV(at32_eic, 0); 662 663/* 664 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this 665 * is always running. 666 */ 667static struct clk at32_pm_pclk = { 668 .name = "pclk", 669 .dev = &at32_pm0_device.dev, 670 .parent = &pbb_clk, 671 .mode = pbb_clk_mode, 672 .get_rate = pbb_clk_get_rate, 673 .users = 1, 674 .index = 0, 675}; 676 677static struct resource intc0_resource[] = { 678 PBMEM(0xfff00400), 679}; 680struct platform_device at32_intc0_device = { 681 .name = "intc", 682 .id = 0, 683 .resource = intc0_resource, 684 .num_resources = ARRAY_SIZE(intc0_resource), 685}; 686DEV_CLK(pclk, at32_intc0, pbb, 1); 687 688static struct clk ebi_clk = { 689 .name = "ebi", 690 .parent = &hsb_clk, 691 .mode = hsb_clk_mode, 692 .get_rate = hsb_clk_get_rate, 693 .users = 1, 694}; 695static struct clk hramc_clk = { 696 .name = "hramc", 697 .parent = &hsb_clk, 698 .mode = hsb_clk_mode, 699 .get_rate = hsb_clk_get_rate, 700 .users = 1, 701 .index = 3, 702}; 703static struct clk sdramc_clk = { 704 .name = "sdramc_clk", 705 .parent = &pbb_clk, 706 .mode = pbb_clk_mode, 707 .get_rate = pbb_clk_get_rate, 708 .users = 1, 709 .index = 14, 710}; 711 712static struct resource smc0_resource[] = { 713 PBMEM(0xfff03400), 714}; 715DEFINE_DEV(smc, 0); 716DEV_CLK(pclk, smc0, pbb, 13); 717DEV_CLK(mck, smc0, hsb, 0); 718 719static struct platform_device pdc_device = { 720 .name = "pdc", 721 .id = 0, 722}; 723DEV_CLK(hclk, pdc, hsb, 4); 724DEV_CLK(pclk, pdc, pba, 16); 725 726static struct clk pico_clk = { 727 .name = "pico", 728 .parent = &cpu_clk, 729 .mode = cpu_clk_mode, 730 .get_rate = cpu_clk_get_rate, 731 .users = 1, 732}; 733 734/* -------------------------------------------------------------------- 735 * HMATRIX 736 * -------------------------------------------------------------------- */ 737 738struct clk at32_hmatrix_clk = { 739 .name = "hmatrix_clk", 740 .parent = &pbb_clk, 741 .mode = pbb_clk_mode, 742 .get_rate = pbb_clk_get_rate, 743 .index = 2, 744 .users = 1, 745}; 746 747/* 748 * Set bits in the HMATRIX Special Function Register (SFR) used by the 749 * External Bus Interface (EBI). This can be used to enable special 750 * features like CompactFlash support, NAND Flash support, etc. on 751 * certain chipselects. 752 */ 753static inline void set_ebi_sfr_bits(u32 mask) 754{ 755 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask); 756} 757 758/* -------------------------------------------------------------------- 759 * Timer/Counter (TC) 760 * -------------------------------------------------------------------- */ 761 762static struct resource at32_tcb0_resource[] = { 763 PBMEM(0xfff00c00), 764 IRQ(22), 765}; 766static struct platform_device at32_tcb0_device = { 767 .name = "atmel_tcb", 768 .id = 0, 769 .resource = at32_tcb0_resource, 770 .num_resources = ARRAY_SIZE(at32_tcb0_resource), 771}; 772DEV_CLK(t0_clk, at32_tcb0, pbb, 3); 773 774static struct resource at32_tcb1_resource[] = { 775 PBMEM(0xfff01000), 776 IRQ(23), 777}; 778static struct platform_device at32_tcb1_device = { 779 .name = "atmel_tcb", 780 .id = 1, 781 .resource = at32_tcb1_resource, 782 .num_resources = ARRAY_SIZE(at32_tcb1_resource), 783}; 784DEV_CLK(t0_clk, at32_tcb1, pbb, 4); 785 786/* -------------------------------------------------------------------- 787 * PIO 788 * -------------------------------------------------------------------- */ 789 790static struct resource pio0_resource[] = { 791 PBMEM(0xffe02800), 792 IRQ(13), 793}; 794DEFINE_DEV(pio, 0); 795DEV_CLK(mck, pio0, pba, 10); 796 797static struct resource pio1_resource[] = { 798 PBMEM(0xffe02c00), 799 IRQ(14), 800}; 801DEFINE_DEV(pio, 1); 802DEV_CLK(mck, pio1, pba, 11); 803 804static struct resource pio2_resource[] = { 805 PBMEM(0xffe03000), 806 IRQ(15), 807}; 808DEFINE_DEV(pio, 2); 809DEV_CLK(mck, pio2, pba, 12); 810 811static struct resource pio3_resource[] = { 812 PBMEM(0xffe03400), 813 IRQ(16), 814}; 815DEFINE_DEV(pio, 3); 816DEV_CLK(mck, pio3, pba, 13); 817 818static struct resource pio4_resource[] = { 819 PBMEM(0xffe03800), 820 IRQ(17), 821}; 822DEFINE_DEV(pio, 4); 823DEV_CLK(mck, pio4, pba, 14); 824 825static int __init system_device_init(void) 826{ 827 platform_device_register(&at32_pm0_device); 828 platform_device_register(&at32_intc0_device); 829 platform_device_register(&at32ap700x_rtc0_device); 830 platform_device_register(&at32_wdt0_device); 831 platform_device_register(&at32_eic0_device); 832 platform_device_register(&smc0_device); 833 platform_device_register(&pdc_device); 834 platform_device_register(&dw_dmac0_device); 835 836 platform_device_register(&at32_tcb0_device); 837 platform_device_register(&at32_tcb1_device); 838 839 platform_device_register(&pio0_device); 840 platform_device_register(&pio1_device); 841 platform_device_register(&pio2_device); 842 platform_device_register(&pio3_device); 843 platform_device_register(&pio4_device); 844 845 return 0; 846} 847core_initcall(system_device_init); 848 849/* -------------------------------------------------------------------- 850 * PSIF 851 * -------------------------------------------------------------------- */ 852static struct resource atmel_psif0_resource[] __initdata = { 853 { 854 .start = 0xffe03c00, 855 .end = 0xffe03cff, 856 .flags = IORESOURCE_MEM, 857 }, 858 IRQ(18), 859}; 860static struct clk atmel_psif0_pclk = { 861 .name = "pclk", 862 .parent = &pba_clk, 863 .mode = pba_clk_mode, 864 .get_rate = pba_clk_get_rate, 865 .index = 15, 866}; 867 868static struct resource atmel_psif1_resource[] __initdata = { 869 { 870 .start = 0xffe03d00, 871 .end = 0xffe03dff, 872 .flags = IORESOURCE_MEM, 873 }, 874 IRQ(18), 875}; 876static struct clk atmel_psif1_pclk = { 877 .name = "pclk", 878 .parent = &pba_clk, 879 .mode = pba_clk_mode, 880 .get_rate = pba_clk_get_rate, 881 .index = 15, 882}; 883 884struct platform_device *__init at32_add_device_psif(unsigned int id) 885{ 886 struct platform_device *pdev; 887 u32 pin_mask; 888 889 if (!(id == 0 || id == 1)) 890 return NULL; 891 892 pdev = platform_device_alloc("atmel_psif", id); 893 if (!pdev) 894 return NULL; 895 896 switch (id) { 897 case 0: 898 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */ 899 900 if (platform_device_add_resources(pdev, atmel_psif0_resource, 901 ARRAY_SIZE(atmel_psif0_resource))) 902 goto err_add_resources; 903 atmel_psif0_pclk.dev = &pdev->dev; 904 select_peripheral(PIOA, pin_mask, PERIPH_A, 0); 905 break; 906 case 1: 907 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */ 908 909 if (platform_device_add_resources(pdev, atmel_psif1_resource, 910 ARRAY_SIZE(atmel_psif1_resource))) 911 goto err_add_resources; 912 atmel_psif1_pclk.dev = &pdev->dev; 913 select_peripheral(PIOB, pin_mask, PERIPH_A, 0); 914 break; 915 default: 916 return NULL; 917 } 918 919 platform_device_add(pdev); 920 return pdev; 921 922err_add_resources: 923 platform_device_put(pdev); 924 return NULL; 925} 926 927/* -------------------------------------------------------------------- 928 * USART 929 * -------------------------------------------------------------------- */ 930 931static struct atmel_uart_data atmel_usart0_data = { 932 .use_dma_tx = 1, 933 .use_dma_rx = 1, 934}; 935static struct resource atmel_usart0_resource[] = { 936 PBMEM(0xffe00c00), 937 IRQ(6), 938}; 939DEFINE_DEV_DATA(atmel_usart, 0); 940DEV_CLK(usart, atmel_usart0, pba, 3); 941 942static struct atmel_uart_data atmel_usart1_data = { 943 .use_dma_tx = 1, 944 .use_dma_rx = 1, 945}; 946static struct resource atmel_usart1_resource[] = { 947 PBMEM(0xffe01000), 948 IRQ(7), 949}; 950DEFINE_DEV_DATA(atmel_usart, 1); 951DEV_CLK(usart, atmel_usart1, pba, 4); 952 953static struct atmel_uart_data atmel_usart2_data = { 954 .use_dma_tx = 1, 955 .use_dma_rx = 1, 956}; 957static struct resource atmel_usart2_resource[] = { 958 PBMEM(0xffe01400), 959 IRQ(8), 960}; 961DEFINE_DEV_DATA(atmel_usart, 2); 962DEV_CLK(usart, atmel_usart2, pba, 5); 963 964static struct atmel_uart_data atmel_usart3_data = { 965 .use_dma_tx = 1, 966 .use_dma_rx = 1, 967}; 968static struct resource atmel_usart3_resource[] = { 969 PBMEM(0xffe01800), 970 IRQ(9), 971}; 972DEFINE_DEV_DATA(atmel_usart, 3); 973DEV_CLK(usart, atmel_usart3, pba, 6); 974 975static inline void configure_usart0_pins(int flags) 976{ 977 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */ 978 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6); 979 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7); 980 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10); 981 982 select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); 983} 984 985static inline void configure_usart1_pins(int flags) 986{ 987 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */ 988 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19); 989 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20); 990 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16); 991 992 select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP); 993} 994 995static inline void configure_usart2_pins(int flags) 996{ 997 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */ 998 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30); 999 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29); 1000 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28); 1001 1002 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); 1003} 1004 1005static inline void configure_usart3_pins(int flags) 1006{ 1007 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */ 1008 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16); 1009 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15); 1010 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19); 1011 1012 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); 1013} 1014 1015static struct platform_device *__initdata at32_usarts[4]; 1016 1017void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags) 1018{ 1019 struct platform_device *pdev; 1020 struct atmel_uart_data *pdata; 1021 1022 switch (hw_id) { 1023 case 0: 1024 pdev = &atmel_usart0_device; 1025 configure_usart0_pins(flags); 1026 break; 1027 case 1: 1028 pdev = &atmel_usart1_device; 1029 configure_usart1_pins(flags); 1030 break; 1031 case 2: 1032 pdev = &atmel_usart2_device; 1033 configure_usart2_pins(flags); 1034 break; 1035 case 3: 1036 pdev = &atmel_usart3_device; 1037 configure_usart3_pins(flags); 1038 break; 1039 default: 1040 return; 1041 } 1042 1043 if (PXSEG(pdev->resource[0].start) == P4SEG) { 1044 /* Addresses in the P4 segment are permanently mapped 1:1 */ 1045 struct atmel_uart_data *data = pdev->dev.platform_data; 1046 data->regs = (void __iomem *)pdev->resource[0].start; 1047 } 1048 1049 pdev->id = line; 1050 pdata = pdev->dev.platform_data; 1051 pdata->num = line; 1052 at32_usarts[line] = pdev; 1053} 1054 1055struct platform_device *__init at32_add_device_usart(unsigned int id) 1056{ 1057 platform_device_register(at32_usarts[id]); 1058 return at32_usarts[id]; 1059} 1060 1061void __init at32_setup_serial_console(unsigned int usart_id) 1062{ 1063#ifdef CONFIG_SERIAL_ATMEL 1064 atmel_default_console_device = at32_usarts[usart_id]; 1065#endif 1066} 1067 1068/* -------------------------------------------------------------------- 1069 * Ethernet 1070 * -------------------------------------------------------------------- */ 1071 1072#ifdef CONFIG_CPU_AT32AP7000 1073static struct macb_platform_data macb0_data; 1074static struct resource macb0_resource[] = { 1075 PBMEM(0xfff01800), 1076 IRQ(25), 1077}; 1078DEFINE_DEV_DATA(macb, 0); 1079DEV_CLK(hclk, macb0, hsb, 8); 1080DEV_CLK(pclk, macb0, pbb, 6); 1081 1082static struct macb_platform_data macb1_data; 1083static struct resource macb1_resource[] = { 1084 PBMEM(0xfff01c00), 1085 IRQ(26), 1086}; 1087DEFINE_DEV_DATA(macb, 1); 1088DEV_CLK(hclk, macb1, hsb, 9); 1089DEV_CLK(pclk, macb1, pbb, 7); 1090 1091struct platform_device *__init 1092at32_add_device_eth(unsigned int id, struct macb_platform_data *data) 1093{ 1094 struct platform_device *pdev; 1095 u32 pin_mask; 1096 1097 switch (id) { 1098 case 0: 1099 pdev = &macb0_device; 1100 1101 pin_mask = (1 << 3); /* TXD0 */ 1102 pin_mask |= (1 << 4); /* TXD1 */ 1103 pin_mask |= (1 << 7); /* TXEN */ 1104 pin_mask |= (1 << 8); /* TXCK */ 1105 pin_mask |= (1 << 9); /* RXD0 */ 1106 pin_mask |= (1 << 10); /* RXD1 */ 1107 pin_mask |= (1 << 13); /* RXER */ 1108 pin_mask |= (1 << 15); /* RXDV */ 1109 pin_mask |= (1 << 16); /* MDC */ 1110 pin_mask |= (1 << 17); /* MDIO */ 1111 1112 if (!data->is_rmii) { 1113 pin_mask |= (1 << 0); /* COL */ 1114 pin_mask |= (1 << 1); /* CRS */ 1115 pin_mask |= (1 << 2); /* TXER */ 1116 pin_mask |= (1 << 5); /* TXD2 */ 1117 pin_mask |= (1 << 6); /* TXD3 */ 1118 pin_mask |= (1 << 11); /* RXD2 */ 1119 pin_mask |= (1 << 12); /* RXD3 */ 1120 pin_mask |= (1 << 14); /* RXCK */ 1121#ifndef CONFIG_BOARD_MIMC200 1122 pin_mask |= (1 << 18); /* SPD */ 1123#endif 1124 } 1125 1126 select_peripheral(PIOC, pin_mask, PERIPH_A, 0); 1127 1128 break; 1129 1130 case 1: 1131 pdev = &macb1_device; 1132 1133 pin_mask = (1 << 13); /* TXD0 */ 1134 pin_mask |= (1 << 14); /* TXD1 */ 1135 pin_mask |= (1 << 11); /* TXEN */ 1136 pin_mask |= (1 << 12); /* TXCK */ 1137 pin_mask |= (1 << 10); /* RXD0 */ 1138 pin_mask |= (1 << 6); /* RXD1 */ 1139 pin_mask |= (1 << 5); /* RXER */ 1140 pin_mask |= (1 << 4); /* RXDV */ 1141 pin_mask |= (1 << 3); /* MDC */ 1142 pin_mask |= (1 << 2); /* MDIO */ 1143 1144#ifndef CONFIG_BOARD_MIMC200 1145 if (!data->is_rmii) 1146 pin_mask |= (1 << 15); /* SPD */ 1147#endif 1148 1149 select_peripheral(PIOD, pin_mask, PERIPH_B, 0); 1150 1151 if (!data->is_rmii) { 1152 pin_mask = (1 << 19); /* COL */ 1153 pin_mask |= (1 << 23); /* CRS */ 1154 pin_mask |= (1 << 26); /* TXER */ 1155 pin_mask |= (1 << 27); /* TXD2 */ 1156 pin_mask |= (1 << 28); /* TXD3 */ 1157 pin_mask |= (1 << 29); /* RXD2 */ 1158 pin_mask |= (1 << 30); /* RXD3 */ 1159 pin_mask |= (1 << 24); /* RXCK */ 1160 1161 select_peripheral(PIOC, pin_mask, PERIPH_B, 0); 1162 } 1163 break; 1164 1165 default: 1166 return NULL; 1167 } 1168 1169 memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data)); 1170 platform_device_register(pdev); 1171 1172 return pdev; 1173} 1174#endif 1175 1176/* -------------------------------------------------------------------- 1177 * SPI 1178 * -------------------------------------------------------------------- */ 1179static struct resource atmel_spi0_resource[] = { 1180 PBMEM(0xffe00000), 1181 IRQ(3), 1182}; 1183DEFINE_DEV(atmel_spi, 0); 1184DEV_CLK(spi_clk, atmel_spi0, pba, 0); 1185 1186static struct resource atmel_spi1_resource[] = { 1187 PBMEM(0xffe00400), 1188 IRQ(4), 1189}; 1190DEFINE_DEV(atmel_spi, 1); 1191DEV_CLK(spi_clk, atmel_spi1, pba, 1); 1192 1193void __init 1194at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n) 1195{ 1196 /* 1197 * Manage the chipselects as GPIOs, normally using the same pins 1198 * the SPI controller expects; but boards can use other pins. 1199 */ 1200 static u8 __initdata spi_pins[][4] = { 1201 { GPIO_PIN_PA(3), GPIO_PIN_PA(4), 1202 GPIO_PIN_PA(5), GPIO_PIN_PA(20) }, 1203 { GPIO_PIN_PB(2), GPIO_PIN_PB(3), 1204 GPIO_PIN_PB(4), GPIO_PIN_PA(27) }, 1205 }; 1206 unsigned int pin, mode; 1207 1208 /* There are only 2 SPI controllers */ 1209 if (bus_num > 1) 1210 return; 1211 1212 for (; n; n--, b++) { 1213 b->bus_num = bus_num; 1214 if (b->chip_select >= 4) 1215 continue; 1216 pin = (unsigned)b->controller_data; 1217 if (!pin) { 1218 pin = spi_pins[bus_num][b->chip_select]; 1219 b->controller_data = (void *)pin; 1220 } 1221 mode = AT32_GPIOF_OUTPUT; 1222 if (!(b->mode & SPI_CS_HIGH)) 1223 mode |= AT32_GPIOF_HIGH; 1224 at32_select_gpio(pin, mode); 1225 } 1226} 1227 1228struct platform_device *__init 1229at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) 1230{ 1231 struct platform_device *pdev; 1232 u32 pin_mask; 1233 1234 switch (id) { 1235 case 0: 1236 pdev = &atmel_spi0_device; 1237 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */ 1238 1239 /* pullup MISO so a level is always defined */ 1240 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP); 1241 select_peripheral(PIOA, pin_mask, PERIPH_A, 0); 1242 1243 at32_spi_setup_slaves(0, b, n); 1244 break; 1245 1246 case 1: 1247 pdev = &atmel_spi1_device; 1248 pin_mask = (1 << 1) | (1 << 5); /* MOSI */ 1249 1250 /* pullup MISO so a level is always defined */ 1251 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP); 1252 select_peripheral(PIOB, pin_mask, PERIPH_B, 0); 1253 1254 at32_spi_setup_slaves(1, b, n); 1255 break; 1256 1257 default: 1258 return NULL; 1259 } 1260 1261 spi_register_board_info(b, n); 1262 platform_device_register(pdev); 1263 return pdev; 1264} 1265 1266/* -------------------------------------------------------------------- 1267 * TWI 1268 * -------------------------------------------------------------------- */ 1269static struct resource atmel_twi0_resource[] __initdata = { 1270 PBMEM(0xffe00800), 1271 IRQ(5), 1272}; 1273static struct clk atmel_twi0_pclk = { 1274 .name = "twi_pclk", 1275 .parent = &pba_clk, 1276 .mode = pba_clk_mode, 1277 .get_rate = pba_clk_get_rate, 1278 .index = 2, 1279}; 1280 1281struct platform_device *__init at32_add_device_twi(unsigned int id, 1282 struct i2c_board_info *b, 1283 unsigned int n) 1284{ 1285 struct platform_device *pdev; 1286 u32 pin_mask; 1287 1288 if (id != 0) 1289 return NULL; 1290 1291 pdev = platform_device_alloc("atmel_twi", id); 1292 if (!pdev) 1293 return NULL; 1294 1295 if (platform_device_add_resources(pdev, atmel_twi0_resource, 1296 ARRAY_SIZE(atmel_twi0_resource))) 1297 goto err_add_resources; 1298 1299 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */ 1300 1301 select_peripheral(PIOA, pin_mask, PERIPH_A, 0); 1302 1303 atmel_twi0_pclk.dev = &pdev->dev; 1304 1305 if (b) 1306 i2c_register_board_info(id, b, n); 1307 1308 platform_device_add(pdev); 1309 return pdev; 1310 1311err_add_resources: 1312 platform_device_put(pdev); 1313 return NULL; 1314} 1315 1316/* -------------------------------------------------------------------- 1317 * MMC 1318 * -------------------------------------------------------------------- */ 1319static struct resource atmel_mci0_resource[] __initdata = { 1320 PBMEM(0xfff02400), 1321 IRQ(28), 1322}; 1323static struct clk atmel_mci0_pclk = { 1324 .name = "mci_clk", 1325 .parent = &pbb_clk, 1326 .mode = pbb_clk_mode, 1327 .get_rate = pbb_clk_get_rate, 1328 .index = 9, 1329}; 1330 1331static bool at32_mci_dma_filter(struct dma_chan *chan, void *pdata) 1332{ 1333 struct mci_dma_data *sl = pdata; 1334 1335 if (!sl) 1336 return false; 1337 1338 if (find_slave_dev(sl) == chan->device->dev) { 1339 chan->private = slave_data_ptr(sl); 1340 return true; 1341 } 1342 1343 return false; 1344} 1345 1346struct platform_device *__init 1347at32_add_device_mci(unsigned int id, struct mci_platform_data *data) 1348{ 1349 struct platform_device *pdev; 1350 struct mci_dma_data *slave; 1351 u32 pioa_mask; 1352 u32 piob_mask; 1353 1354 if (id != 0 || !data) 1355 return NULL; 1356 1357 /* Must have at least one usable slot */ 1358 if (!data->slot[0].bus_width && !data->slot[1].bus_width) 1359 return NULL; 1360 1361 pdev = platform_device_alloc("atmel_mci", id); 1362 if (!pdev) 1363 goto fail; 1364 1365 if (platform_device_add_resources(pdev, atmel_mci0_resource, 1366 ARRAY_SIZE(atmel_mci0_resource))) 1367 goto fail; 1368 1369 slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL); 1370 if (!slave) 1371 goto fail; 1372 1373 slave->sdata.dma_dev = &dw_dmac0_device.dev; 1374 slave->sdata.src_id = 0; 1375 slave->sdata.dst_id = 1; 1376 slave->sdata.src_master = 1; 1377 slave->sdata.dst_master = 0; 1378 1379 data->dma_slave = slave; 1380 data->dma_filter = at32_mci_dma_filter; 1381 1382 if (platform_device_add_data(pdev, data, 1383 sizeof(struct mci_platform_data))) 1384 goto fail_free; 1385 1386 /* CLK line is common to both slots */ 1387 pioa_mask = 1 << 10; 1388 1389 switch (data->slot[0].bus_width) { 1390 case 4: 1391 pioa_mask |= 1 << 13; /* DATA1 */ 1392 pioa_mask |= 1 << 14; /* DATA2 */ 1393 pioa_mask |= 1 << 15; /* DATA3 */ 1394 /* fall through */ 1395 case 1: 1396 pioa_mask |= 1 << 11; /* CMD */ 1397 pioa_mask |= 1 << 12; /* DATA0 */ 1398 1399 if (gpio_is_valid(data->slot[0].detect_pin)) 1400 at32_select_gpio(data->slot[0].detect_pin, 0); 1401 if (gpio_is_valid(data->slot[0].wp_pin)) 1402 at32_select_gpio(data->slot[0].wp_pin, 0); 1403 break; 1404 case 0: 1405 /* Slot is unused */ 1406 break; 1407 default: 1408 goto fail_free; 1409 } 1410 1411 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0); 1412 piob_mask = 0; 1413 1414 switch (data->slot[1].bus_width) { 1415 case 4: 1416 piob_mask |= 1 << 8; /* DATA1 */ 1417 piob_mask |= 1 << 9; /* DATA2 */ 1418 piob_mask |= 1 << 10; /* DATA3 */ 1419 /* fall through */ 1420 case 1: 1421 piob_mask |= 1 << 6; /* CMD */ 1422 piob_mask |= 1 << 7; /* DATA0 */ 1423 select_peripheral(PIOB, piob_mask, PERIPH_B, 0); 1424 1425 if (gpio_is_valid(data->slot[1].detect_pin)) 1426 at32_select_gpio(data->slot[1].detect_pin, 0); 1427 if (gpio_is_valid(data->slot[1].wp_pin)) 1428 at32_select_gpio(data->slot[1].wp_pin, 0); 1429 break; 1430 case 0: 1431 /* Slot is unused */ 1432 break; 1433 default: 1434 if (!data->slot[0].bus_width) 1435 goto fail_free; 1436 1437 data->slot[1].bus_width = 0; 1438 break; 1439 } 1440 1441 atmel_mci0_pclk.dev = &pdev->dev; 1442 1443 platform_device_add(pdev); 1444 return pdev; 1445 1446fail_free: 1447 kfree(slave); 1448fail: 1449 data->dma_slave = NULL; 1450 platform_device_put(pdev); 1451 return NULL; 1452} 1453 1454/* -------------------------------------------------------------------- 1455 * LCDC 1456 * -------------------------------------------------------------------- */ 1457#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) 1458static struct atmel_lcdfb_pdata atmel_lcdfb0_data; 1459static struct resource atmel_lcdfb0_resource[] = { 1460 { 1461 .start = 0xff000000, 1462 .end = 0xff000fff, 1463 .flags = IORESOURCE_MEM, 1464 }, 1465 IRQ(1), 1466 { 1467 /* Placeholder for pre-allocated fb memory */ 1468 .start = 0x00000000, 1469 .end = 0x00000000, 1470 .flags = 0, 1471 }, 1472}; 1473DEFINE_DEV_DATA(atmel_lcdfb, 0); 1474DEV_CLK(hclk, atmel_lcdfb0, hsb, 7); 1475static struct clk atmel_lcdfb0_pixclk = { 1476 .name = "lcdc_clk", 1477 .dev = &atmel_lcdfb0_device.dev, 1478 .mode = genclk_mode, 1479 .get_rate = genclk_get_rate, 1480 .set_rate = genclk_set_rate, 1481 .set_parent = genclk_set_parent, 1482 .index = 7, 1483}; 1484 1485struct platform_device *__init 1486at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data, 1487 unsigned long fbmem_start, unsigned long fbmem_len, 1488 u64 pin_mask) 1489{ 1490 struct platform_device *pdev; 1491 struct atmel_lcdfb_pdata *info; 1492 struct fb_monspecs *monspecs; 1493 struct fb_videomode *modedb; 1494 unsigned int modedb_size; 1495 u32 portc_mask, portd_mask, porte_mask; 1496 1497 /* 1498 * Do a deep copy of the fb data, monspecs and modedb. Make 1499 * sure all allocations are done before setting up the 1500 * portmux. 1501 */ 1502 monspecs = kmemdup(data->default_monspecs, 1503 sizeof(struct fb_monspecs), GFP_KERNEL); 1504 if (!monspecs) 1505 return NULL; 1506 1507 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len; 1508 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL); 1509 if (!modedb) 1510 goto err_dup_modedb; 1511 monspecs->modedb = modedb; 1512 1513 switch (id) { 1514 case 0: 1515 pdev = &atmel_lcdfb0_device; 1516 1517 if (pin_mask == 0ULL) 1518 /* Default to "full" lcdc control signals and 24bit */ 1519 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL; 1520 1521 /* LCDC on port C */ 1522 portc_mask = pin_mask & 0xfff80000; 1523 select_peripheral(PIOC, portc_mask, PERIPH_A, 0); 1524 1525 /* LCDC on port D */ 1526 portd_mask = pin_mask & 0x0003ffff; 1527 select_peripheral(PIOD, portd_mask, PERIPH_A, 0); 1528 1529 /* LCDC on port E */ 1530 porte_mask = (pin_mask >> 32) & 0x0007ffff; 1531 select_peripheral(PIOE, porte_mask, PERIPH_B, 0); 1532 1533 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); 1534 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); 1535 break; 1536 1537 default: 1538 goto err_invalid_id; 1539 } 1540 1541 if (fbmem_len) { 1542 pdev->resource[2].start = fbmem_start; 1543 pdev->resource[2].end = fbmem_start + fbmem_len - 1; 1544 pdev->resource[2].flags = IORESOURCE_MEM; 1545 } 1546 1547 info = pdev->dev.platform_data; 1548 memcpy(info, data, sizeof(struct atmel_lcdfb_pdata)); 1549 info->default_monspecs = monspecs; 1550 1551 pdev->name = "at32ap-lcdfb"; 1552 1553 platform_device_register(pdev); 1554 return pdev; 1555 1556err_invalid_id: 1557 kfree(modedb); 1558err_dup_modedb: 1559 kfree(monspecs); 1560 return NULL; 1561} 1562#endif 1563 1564/* -------------------------------------------------------------------- 1565 * PWM 1566 * -------------------------------------------------------------------- */ 1567static struct resource atmel_pwm0_resource[] __initdata = { 1568 PBMEM(0xfff01400), 1569 IRQ(24), 1570}; 1571static struct clk atmel_pwm0_mck = { 1572 .name = "at91sam9rl-pwm", 1573 .parent = &pbb_clk, 1574 .mode = pbb_clk_mode, 1575 .get_rate = pbb_clk_get_rate, 1576 .index = 5, 1577}; 1578 1579struct platform_device *__init at32_add_device_pwm(u32 mask) 1580{ 1581 struct platform_device *pdev; 1582 u32 pin_mask; 1583 1584 if (!mask) 1585 return NULL; 1586 1587 pdev = platform_device_alloc("at91sam9rl-pwm", 0); 1588 if (!pdev) 1589 return NULL; 1590 1591 if (platform_device_add_resources(pdev, atmel_pwm0_resource, 1592 ARRAY_SIZE(atmel_pwm0_resource))) 1593 goto out_free_pdev; 1594 1595 pin_mask = 0; 1596 if (mask & (1 << 0)) 1597 pin_mask |= (1 << 28); 1598 if (mask & (1 << 1)) 1599 pin_mask |= (1 << 29); 1600 if (pin_mask > 0) 1601 select_peripheral(PIOA, pin_mask, PERIPH_A, 0); 1602 1603 pin_mask = 0; 1604 if (mask & (1 << 2)) 1605 pin_mask |= (1 << 21); 1606 if (mask & (1 << 3)) 1607 pin_mask |= (1 << 22); 1608 if (pin_mask > 0) 1609 select_peripheral(PIOA, pin_mask, PERIPH_B, 0); 1610 1611 atmel_pwm0_mck.dev = &pdev->dev; 1612 1613 platform_device_add(pdev); 1614 1615 return pdev; 1616 1617out_free_pdev: 1618 platform_device_put(pdev); 1619 return NULL; 1620} 1621 1622/* -------------------------------------------------------------------- 1623 * SSC 1624 * -------------------------------------------------------------------- */ 1625static struct resource ssc0_resource[] = { 1626 PBMEM(0xffe01c00), 1627 IRQ(10), 1628}; 1629DEFINE_DEV(ssc, 0); 1630DEV_CLK(pclk, ssc0, pba, 7); 1631 1632static struct resource ssc1_resource[] = { 1633 PBMEM(0xffe02000), 1634 IRQ(11), 1635}; 1636DEFINE_DEV(ssc, 1); 1637DEV_CLK(pclk, ssc1, pba, 8); 1638 1639static struct resource ssc2_resource[] = { 1640 PBMEM(0xffe02400), 1641 IRQ(12), 1642}; 1643DEFINE_DEV(ssc, 2); 1644DEV_CLK(pclk, ssc2, pba, 9); 1645 1646struct platform_device *__init 1647at32_add_device_ssc(unsigned int id, unsigned int flags) 1648{ 1649 struct platform_device *pdev; 1650 u32 pin_mask = 0; 1651 1652 switch (id) { 1653 case 0: 1654 pdev = &ssc0_device; 1655 if (flags & ATMEL_SSC_RF) 1656 pin_mask |= (1 << 21); /* RF */ 1657 if (flags & ATMEL_SSC_RK) 1658 pin_mask |= (1 << 22); /* RK */ 1659 if (flags & ATMEL_SSC_TK) 1660 pin_mask |= (1 << 23); /* TK */ 1661 if (flags & ATMEL_SSC_TF) 1662 pin_mask |= (1 << 24); /* TF */ 1663 if (flags & ATMEL_SSC_TD) 1664 pin_mask |= (1 << 25); /* TD */ 1665 if (flags & ATMEL_SSC_RD) 1666 pin_mask |= (1 << 26); /* RD */ 1667 1668 if (pin_mask > 0) 1669 select_peripheral(PIOA, pin_mask, PERIPH_A, 0); 1670 1671 break; 1672 case 1: 1673 pdev = &ssc1_device; 1674 if (flags & ATMEL_SSC_RF) 1675 pin_mask |= (1 << 0); /* RF */ 1676 if (flags & ATMEL_SSC_RK) 1677 pin_mask |= (1 << 1); /* RK */ 1678 if (flags & ATMEL_SSC_TK) 1679 pin_mask |= (1 << 2); /* TK */ 1680 if (flags & ATMEL_SSC_TF) 1681 pin_mask |= (1 << 3); /* TF */ 1682 if (flags & ATMEL_SSC_TD) 1683 pin_mask |= (1 << 4); /* TD */ 1684 if (flags & ATMEL_SSC_RD) 1685 pin_mask |= (1 << 5); /* RD */ 1686 1687 if (pin_mask > 0) 1688 select_peripheral(PIOA, pin_mask, PERIPH_B, 0); 1689 1690 break; 1691 case 2: 1692 pdev = &ssc2_device; 1693 if (flags & ATMEL_SSC_TD) 1694 pin_mask |= (1 << 13); /* TD */ 1695 if (flags & ATMEL_SSC_RD) 1696 pin_mask |= (1 << 14); /* RD */ 1697 if (flags & ATMEL_SSC_TK) 1698 pin_mask |= (1 << 15); /* TK */ 1699 if (flags & ATMEL_SSC_TF) 1700 pin_mask |= (1 << 16); /* TF */ 1701 if (flags & ATMEL_SSC_RF) 1702 pin_mask |= (1 << 17); /* RF */ 1703 if (flags & ATMEL_SSC_RK) 1704 pin_mask |= (1 << 18); /* RK */ 1705 1706 if (pin_mask > 0) 1707 select_peripheral(PIOB, pin_mask, PERIPH_A, 0); 1708 1709 break; 1710 default: 1711 return NULL; 1712 } 1713 1714 platform_device_register(pdev); 1715 return pdev; 1716} 1717 1718/* -------------------------------------------------------------------- 1719 * USB Device Controller 1720 * -------------------------------------------------------------------- */ 1721static struct resource usba0_resource[] __initdata = { 1722 { 1723 .start = 0xff300000, 1724 .end = 0xff3fffff, 1725 .flags = IORESOURCE_MEM, 1726 }, { 1727 .start = 0xfff03000, 1728 .end = 0xfff033ff, 1729 .flags = IORESOURCE_MEM, 1730 }, 1731 IRQ(31), 1732}; 1733static struct clk usba0_pclk = { 1734 .name = "pclk", 1735 .parent = &pbb_clk, 1736 .mode = pbb_clk_mode, 1737 .get_rate = pbb_clk_get_rate, 1738 .index = 12, 1739}; 1740static struct clk usba0_hclk = { 1741 .name = "hclk", 1742 .parent = &hsb_clk, 1743 .mode = hsb_clk_mode, 1744 .get_rate = hsb_clk_get_rate, 1745 .index = 6, 1746}; 1747 1748#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ 1749 [idx] = { \ 1750 .name = nam, \ 1751 .index = idx, \ 1752 .fifo_size = maxpkt, \ 1753 .nr_banks = maxbk, \ 1754 .can_dma = dma, \ 1755 .can_isoc = isoc, \ 1756 } 1757 1758static struct usba_ep_data at32_usba_ep[] __initdata = { 1759 EP("ep0", 0, 64, 1, 0, 0), 1760 EP("ep1", 1, 512, 2, 1, 1), 1761 EP("ep2", 2, 512, 2, 1, 1), 1762 EP("ep3-int", 3, 64, 3, 1, 0), 1763 EP("ep4-int", 4, 64, 3, 1, 0), 1764 EP("ep5", 5, 1024, 3, 1, 1), 1765 EP("ep6", 6, 1024, 3, 1, 1), 1766}; 1767 1768#undef EP 1769 1770struct platform_device *__init 1771at32_add_device_usba(unsigned int id, struct usba_platform_data *data) 1772{ 1773 /* 1774 * pdata doesn't have room for any endpoints, so we need to 1775 * append room for the ones we need right after it. 1776 */ 1777 struct { 1778 struct usba_platform_data pdata; 1779 struct usba_ep_data ep[7]; 1780 } usba_data; 1781 struct platform_device *pdev; 1782 1783 if (id != 0) 1784 return NULL; 1785 1786 pdev = platform_device_alloc("atmel_usba_udc", 0); 1787 if (!pdev) 1788 return NULL; 1789 1790 if (platform_device_add_resources(pdev, usba0_resource, 1791 ARRAY_SIZE(usba0_resource))) 1792 goto out_free_pdev; 1793 1794 if (data) { 1795 usba_data.pdata.vbus_pin = data->vbus_pin; 1796 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted; 1797 } else { 1798 usba_data.pdata.vbus_pin = -EINVAL; 1799 usba_data.pdata.vbus_pin_inverted = -EINVAL; 1800 } 1801 1802 data = &usba_data.pdata; 1803 data->num_ep = ARRAY_SIZE(at32_usba_ep); 1804 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep)); 1805 1806 if (platform_device_add_data(pdev, data, sizeof(usba_data))) 1807 goto out_free_pdev; 1808 1809 if (gpio_is_valid(data->vbus_pin)) 1810 at32_select_gpio(data->vbus_pin, 0); 1811 1812 usba0_pclk.dev = &pdev->dev; 1813 usba0_hclk.dev = &pdev->dev; 1814 1815 platform_device_add(pdev); 1816 1817 return pdev; 1818 1819out_free_pdev: 1820 platform_device_put(pdev); 1821 return NULL; 1822} 1823 1824/* -------------------------------------------------------------------- 1825 * IDE / CompactFlash 1826 * -------------------------------------------------------------------- */ 1827#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001) 1828static struct resource at32_smc_cs4_resource[] __initdata = { 1829 { 1830 .start = 0x04000000, 1831 .end = 0x07ffffff, 1832 .flags = IORESOURCE_MEM, 1833 }, 1834 IRQ(~0UL), /* Magic IRQ will be overridden */ 1835}; 1836static struct resource at32_smc_cs5_resource[] __initdata = { 1837 { 1838 .start = 0x20000000, 1839 .end = 0x23ffffff, 1840 .flags = IORESOURCE_MEM, 1841 }, 1842 IRQ(~0UL), /* Magic IRQ will be overridden */ 1843}; 1844 1845static int __init at32_init_ide_or_cf(struct platform_device *pdev, 1846 unsigned int cs, unsigned int extint) 1847{ 1848 static unsigned int extint_pin_map[4] __initdata = { 1849 (1 << 25), 1850 (1 << 26), 1851 (1 << 27), 1852 (1 << 28), 1853 }; 1854 static bool common_pins_initialized __initdata = false; 1855 unsigned int extint_pin; 1856 int ret; 1857 u32 pin_mask; 1858 1859 if (extint >= ARRAY_SIZE(extint_pin_map)) 1860 return -EINVAL; 1861 extint_pin = extint_pin_map[extint]; 1862 1863 switch (cs) { 1864 case 4: 1865 ret = platform_device_add_resources(pdev, 1866 at32_smc_cs4_resource, 1867 ARRAY_SIZE(at32_smc_cs4_resource)); 1868 if (ret) 1869 return ret; 1870 1871 /* NCS4 -> OE_N */ 1872 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0); 1873 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE); 1874 break; 1875 case 5: 1876 ret = platform_device_add_resources(pdev, 1877 at32_smc_cs5_resource, 1878 ARRAY_SIZE(at32_smc_cs5_resource)); 1879 if (ret) 1880 return ret; 1881 1882 /* NCS5 -> OE_N */ 1883 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0); 1884 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE); 1885 break; 1886 default: 1887 return -EINVAL; 1888 } 1889 1890 if (!common_pins_initialized) { 1891 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */ 1892 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */ 1893 pin_mask |= (1 << 23); /* CFRNW -> DIR */ 1894 pin_mask |= (1 << 24); /* NWAIT <- IORDY */ 1895 1896 select_peripheral(PIOE, pin_mask, PERIPH_A, 0); 1897 1898 common_pins_initialized = true; 1899 } 1900 1901 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH); 1902 1903 pdev->resource[1].start = EIM_IRQ_BASE + extint; 1904 pdev->resource[1].end = pdev->resource[1].start; 1905 1906 return 0; 1907} 1908 1909struct platform_device *__init 1910at32_add_device_ide(unsigned int id, unsigned int extint, 1911 struct ide_platform_data *data) 1912{ 1913 struct platform_device *pdev; 1914 1915 pdev = platform_device_alloc("at32_ide", id); 1916 if (!pdev) 1917 goto fail; 1918 1919 if (platform_device_add_data(pdev, data, 1920 sizeof(struct ide_platform_data))) 1921 goto fail; 1922 1923 if (at32_init_ide_or_cf(pdev, data->cs, extint)) 1924 goto fail; 1925 1926 platform_device_add(pdev); 1927 return pdev; 1928 1929fail: 1930 platform_device_put(pdev); 1931 return NULL; 1932} 1933 1934struct platform_device *__init 1935at32_add_device_cf(unsigned int id, unsigned int extint, 1936 struct cf_platform_data *data) 1937{ 1938 struct platform_device *pdev; 1939 1940 pdev = platform_device_alloc("at32_cf", id); 1941 if (!pdev) 1942 goto fail; 1943 1944 if (platform_device_add_data(pdev, data, 1945 sizeof(struct cf_platform_data))) 1946 goto fail; 1947 1948 if (at32_init_ide_or_cf(pdev, data->cs, extint)) 1949 goto fail; 1950 1951 if (gpio_is_valid(data->detect_pin)) 1952 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH); 1953 if (gpio_is_valid(data->reset_pin)) 1954 at32_select_gpio(data->reset_pin, 0); 1955 if (gpio_is_valid(data->vcc_pin)) 1956 at32_select_gpio(data->vcc_pin, 0); 1957 /* READY is used as extint, so we can't select it as gpio */ 1958 1959 platform_device_add(pdev); 1960 return pdev; 1961 1962fail: 1963 platform_device_put(pdev); 1964 return NULL; 1965} 1966#endif 1967 1968/* -------------------------------------------------------------------- 1969 * NAND Flash / SmartMedia 1970 * -------------------------------------------------------------------- */ 1971static struct resource smc_cs3_resource[] __initdata = { 1972 { 1973 .start = 0x0c000000, 1974 .end = 0x0fffffff, 1975 .flags = IORESOURCE_MEM, 1976 }, { 1977 .start = 0xfff03c00, 1978 .end = 0xfff03fff, 1979 .flags = IORESOURCE_MEM, 1980 }, 1981}; 1982 1983struct platform_device *__init 1984at32_add_device_nand(unsigned int id, struct atmel_nand_data *data) 1985{ 1986 struct platform_device *pdev; 1987 1988 if (id != 0 || !data) 1989 return NULL; 1990 1991 pdev = platform_device_alloc("atmel_nand", id); 1992 if (!pdev) 1993 goto fail; 1994 1995 if (platform_device_add_resources(pdev, smc_cs3_resource, 1996 ARRAY_SIZE(smc_cs3_resource))) 1997 goto fail; 1998 1999 /* For at32ap7000, we use the reset workaround for nand driver */ 2000 data->need_reset_workaround = true; 2001 2002 if (platform_device_add_data(pdev, data, 2003 sizeof(struct atmel_nand_data))) 2004 goto fail; 2005 2006 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE); 2007 if (data->enable_pin) 2008 at32_select_gpio(data->enable_pin, 2009 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); 2010 if (data->rdy_pin) 2011 at32_select_gpio(data->rdy_pin, 0); 2012 if (data->det_pin) 2013 at32_select_gpio(data->det_pin, 0); 2014 2015 platform_device_add(pdev); 2016 return pdev; 2017 2018fail: 2019 platform_device_put(pdev); 2020 return NULL; 2021} 2022 2023/* -------------------------------------------------------------------- 2024 * AC97C 2025 * -------------------------------------------------------------------- */ 2026static struct resource atmel_ac97c0_resource[] __initdata = { 2027 PBMEM(0xfff02800), 2028 IRQ(29), 2029}; 2030static struct clk atmel_ac97c0_pclk = { 2031 .name = "pclk", 2032 .parent = &pbb_clk, 2033 .mode = pbb_clk_mode, 2034 .get_rate = pbb_clk_get_rate, 2035 .index = 10, 2036}; 2037 2038struct platform_device *__init 2039at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data, 2040 unsigned int flags) 2041{ 2042 struct platform_device *pdev; 2043 struct dw_dma_slave *rx_dws; 2044 struct dw_dma_slave *tx_dws; 2045 struct ac97c_platform_data _data; 2046 u32 pin_mask; 2047 2048 if (id != 0) 2049 return NULL; 2050 2051 pdev = platform_device_alloc("atmel_ac97c", id); 2052 if (!pdev) 2053 return NULL; 2054 2055 if (platform_device_add_resources(pdev, atmel_ac97c0_resource, 2056 ARRAY_SIZE(atmel_ac97c0_resource))) 2057 goto out_free_resources; 2058 2059 if (!data) { 2060 data = &_data; 2061 memset(data, 0, sizeof(struct ac97c_platform_data)); 2062 data->reset_pin = -ENODEV; 2063 } 2064 2065 rx_dws = &data->rx_dws; 2066 tx_dws = &data->tx_dws; 2067 2068 /* Check if DMA slave interface for capture should be configured. */ 2069 if (flags & AC97C_CAPTURE) { 2070 rx_dws->dma_dev = &dw_dmac0_device.dev; 2071 rx_dws->src_id = 3; 2072 rx_dws->src_master = 0; 2073 rx_dws->dst_master = 1; 2074 } 2075 2076 /* Check if DMA slave interface for playback should be configured. */ 2077 if (flags & AC97C_PLAYBACK) { 2078 tx_dws->dma_dev = &dw_dmac0_device.dev; 2079 tx_dws->dst_id = 4; 2080 tx_dws->src_master = 0; 2081 tx_dws->dst_master = 1; 2082 } 2083 2084 if (platform_device_add_data(pdev, data, 2085 sizeof(struct ac97c_platform_data))) 2086 goto out_free_resources; 2087 2088 /* SDO | SYNC | SCLK | SDI */ 2089 pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23); 2090 2091 select_peripheral(PIOB, pin_mask, PERIPH_B, 0); 2092 2093 if (gpio_is_valid(data->reset_pin)) 2094 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT 2095 | AT32_GPIOF_HIGH); 2096 2097 atmel_ac97c0_pclk.dev = &pdev->dev; 2098 2099 platform_device_add(pdev); 2100 return pdev; 2101 2102out_free_resources: 2103 platform_device_put(pdev); 2104 return NULL; 2105} 2106 2107/* -------------------------------------------------------------------- 2108 * ABDAC 2109 * -------------------------------------------------------------------- */ 2110static struct resource abdac0_resource[] __initdata = { 2111 PBMEM(0xfff02000), 2112 IRQ(27), 2113}; 2114static struct clk abdac0_pclk = { 2115 .name = "pclk", 2116 .parent = &pbb_clk, 2117 .mode = pbb_clk_mode, 2118 .get_rate = pbb_clk_get_rate, 2119 .index = 8, 2120}; 2121static struct clk abdac0_sample_clk = { 2122 .name = "sample_clk", 2123 .mode = genclk_mode, 2124 .get_rate = genclk_get_rate, 2125 .set_rate = genclk_set_rate, 2126 .set_parent = genclk_set_parent, 2127 .index = 6, 2128}; 2129 2130struct platform_device *__init 2131at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data) 2132{ 2133 struct platform_device *pdev; 2134 struct dw_dma_slave *dws; 2135 u32 pin_mask; 2136 2137 if (id != 0 || !data) 2138 return NULL; 2139 2140 pdev = platform_device_alloc("atmel_abdac", id); 2141 if (!pdev) 2142 return NULL; 2143 2144 if (platform_device_add_resources(pdev, abdac0_resource, 2145 ARRAY_SIZE(abdac0_resource))) 2146 goto out_free_resources; 2147 2148 dws = &data->dws; 2149 2150 dws->dma_dev = &dw_dmac0_device.dev; 2151 dws->dst_id = 2; 2152 dws->src_master = 0; 2153 dws->dst_master = 1; 2154 2155 if (platform_device_add_data(pdev, data, 2156 sizeof(struct atmel_abdac_pdata))) 2157 goto out_free_resources; 2158 2159 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */ 2160 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */ 2161 2162 select_peripheral(PIOB, pin_mask, PERIPH_A, 0); 2163 2164 abdac0_pclk.dev = &pdev->dev; 2165 abdac0_sample_clk.dev = &pdev->dev; 2166 2167 platform_device_add(pdev); 2168 return pdev; 2169 2170out_free_resources: 2171 platform_device_put(pdev); 2172 return NULL; 2173} 2174 2175/* -------------------------------------------------------------------- 2176 * GCLK 2177 * -------------------------------------------------------------------- */ 2178static struct clk gclk0 = { 2179 .name = "gclk0", 2180 .mode = genclk_mode, 2181 .get_rate = genclk_get_rate, 2182 .set_rate = genclk_set_rate, 2183 .set_parent = genclk_set_parent, 2184 .index = 0, 2185}; 2186static struct clk gclk1 = { 2187 .name = "gclk1", 2188 .mode = genclk_mode, 2189 .get_rate = genclk_get_rate, 2190 .set_rate = genclk_set_rate, 2191 .set_parent = genclk_set_parent, 2192 .index = 1, 2193}; 2194static struct clk gclk2 = { 2195 .name = "gclk2", 2196 .mode = genclk_mode, 2197 .get_rate = genclk_get_rate, 2198 .set_rate = genclk_set_rate, 2199 .set_parent = genclk_set_parent, 2200 .index = 2, 2201}; 2202static struct clk gclk3 = { 2203 .name = "gclk3", 2204 .mode = genclk_mode, 2205 .get_rate = genclk_get_rate, 2206 .set_rate = genclk_set_rate, 2207 .set_parent = genclk_set_parent, 2208 .index = 3, 2209}; 2210static struct clk gclk4 = { 2211 .name = "gclk4", 2212 .mode = genclk_mode, 2213 .get_rate = genclk_get_rate, 2214 .set_rate = genclk_set_rate, 2215 .set_parent = genclk_set_parent, 2216 .index = 4, 2217}; 2218 2219static __initdata struct clk *init_clocks[] = { 2220 &osc32k, 2221 &osc0, 2222 &osc1, 2223 &pll0, 2224 &pll1, 2225 &cpu_clk, 2226 &hsb_clk, 2227 &pba_clk, 2228 &pbb_clk, 2229 &at32_pm_pclk, 2230 &at32_intc0_pclk, 2231 &at32_hmatrix_clk, 2232 &ebi_clk, 2233 &hramc_clk, 2234 &sdramc_clk, 2235 &smc0_pclk, 2236 &smc0_mck, 2237 &pdc_hclk, 2238 &pdc_pclk, 2239 &dw_dmac0_hclk, 2240 &pico_clk, 2241 &pio0_mck, 2242 &pio1_mck, 2243 &pio2_mck, 2244 &pio3_mck, 2245 &pio4_mck, 2246 &at32_tcb0_t0_clk, 2247 &at32_tcb1_t0_clk, 2248 &atmel_psif0_pclk, 2249 &atmel_psif1_pclk, 2250 &atmel_usart0_usart, 2251 &atmel_usart1_usart, 2252 &atmel_usart2_usart, 2253 &atmel_usart3_usart, 2254 &atmel_pwm0_mck, 2255#if defined(CONFIG_CPU_AT32AP7000) 2256 &macb0_hclk, 2257 &macb0_pclk, 2258 &macb1_hclk, 2259 &macb1_pclk, 2260#endif 2261 &atmel_spi0_spi_clk, 2262 &atmel_spi1_spi_clk, 2263 &atmel_twi0_pclk, 2264 &atmel_mci0_pclk, 2265#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) 2266 &atmel_lcdfb0_hclk, 2267 &atmel_lcdfb0_pixclk, 2268#endif 2269 &ssc0_pclk, 2270 &ssc1_pclk, 2271 &ssc2_pclk, 2272 &usba0_hclk, 2273 &usba0_pclk, 2274 &atmel_ac97c0_pclk, 2275 &abdac0_pclk, 2276 &abdac0_sample_clk, 2277 &gclk0, 2278 &gclk1, 2279 &gclk2, 2280 &gclk3, 2281 &gclk4, 2282}; 2283 2284void __init setup_platform(void) 2285{ 2286 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; 2287 int i; 2288 2289 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { 2290 main_clock = &pll0; 2291 cpu_clk.parent = &pll0; 2292 } else { 2293 main_clock = &osc0; 2294 cpu_clk.parent = &osc0; 2295 } 2296 2297 if (pm_readl(PLL0) & PM_BIT(PLLOSC)) 2298 pll0.parent = &osc1; 2299 if (pm_readl(PLL1) & PM_BIT(PLLOSC)) 2300 pll1.parent = &osc1; 2301 2302 genclk_init_parent(&gclk0); 2303 genclk_init_parent(&gclk1); 2304 genclk_init_parent(&gclk2); 2305 genclk_init_parent(&gclk3); 2306 genclk_init_parent(&gclk4); 2307#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) 2308 genclk_init_parent(&atmel_lcdfb0_pixclk); 2309#endif 2310 genclk_init_parent(&abdac0_sample_clk); 2311 2312 /* 2313 * Build initial dynamic clock list by registering all clocks 2314 * from the array. 2315 * At the same time, turn on all clocks that have at least one 2316 * user already, and turn off everything else. We only do this 2317 * for module clocks, and even though it isn't particularly 2318 * pretty to check the address of the mode function, it should 2319 * do the trick... 2320 */ 2321 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) { 2322 struct clk *clk = init_clocks[i]; 2323 2324 /* first, register clock */ 2325 at32_clk_register(clk); 2326 2327 if (clk->users == 0) 2328 continue; 2329 2330 if (clk->mode == &cpu_clk_mode) 2331 cpu_mask |= 1 << clk->index; 2332 else if (clk->mode == &hsb_clk_mode) 2333 hsb_mask |= 1 << clk->index; 2334 else if (clk->mode == &pba_clk_mode) 2335 pba_mask |= 1 << clk->index; 2336 else if (clk->mode == &pbb_clk_mode) 2337 pbb_mask |= 1 << clk->index; 2338 } 2339 2340 pm_writel(CPU_MASK, cpu_mask); 2341 pm_writel(HSB_MASK, hsb_mask); 2342 pm_writel(PBA_MASK, pba_mask); 2343 pm_writel(PBB_MASK, pbb_mask); 2344 2345 /* Initialize the port muxes */ 2346 at32_init_pio(&pio0_device); 2347 at32_init_pio(&pio1_device); 2348 at32_init_pio(&pio2_device); 2349 at32_init_pio(&pio3_device); 2350 at32_init_pio(&pio4_device); 2351} 2352 2353struct gen_pool *sram_pool; 2354 2355static int __init sram_init(void) 2356{ 2357 struct gen_pool *pool; 2358 2359 /* 1KiB granularity */ 2360 pool = gen_pool_create(10, -1); 2361 if (!pool) 2362 goto fail; 2363 2364 if (gen_pool_add(pool, 0x24000000, 0x8000, -1)) 2365 goto err_pool_add; 2366 2367 sram_pool = pool; 2368 return 0; 2369 2370err_pool_add: 2371 gen_pool_destroy(pool); 2372fail: 2373 pr_err("Failed to create SRAM pool\n"); 2374 return -ENOMEM; 2375} 2376core_initcall(sram_init); 2377