1/* 2 * Copyright 2004-2009 Analog Devices Inc. 3 * 2005 National ICT Australia (NICTA) 4 * Aidan Williams <aidan@nicta.com.au> 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9#include <linux/device.h> 10#include <linux/export.h> 11#include <linux/platform_device.h> 12#include <linux/mtd/mtd.h> 13#include <linux/mtd/partitions.h> 14#include <linux/mtd/physmap.h> 15#include <linux/spi/spi.h> 16#include <linux/spi/flash.h> 17 18#include <linux/i2c.h> 19#include <linux/irq.h> 20#include <linux/interrupt.h> 21#include <asm/dma.h> 22#include <asm/bfin5xx_spi.h> 23#include <asm/reboot.h> 24#include <asm/portmux.h> 25#include <asm/dpmc.h> 26#include <asm/bfin_sdh.h> 27#include <linux/spi/ad7877.h> 28#include <net/dsa.h> 29 30/* 31 * Name the Board for the /proc/cpuinfo 32 */ 33const char bfin_board_name[] = "ADI BF518F-EZBRD"; 34 35/* 36 * Driver needs to know address, irq and flag pin. 37 */ 38 39#if IS_ENABLED(CONFIG_MTD_PHYSMAP) 40static struct mtd_partition ezbrd_partitions[] = { 41 { 42 .name = "bootloader(nor)", 43 .size = 0x40000, 44 .offset = 0, 45 }, { 46 .name = "linux kernel(nor)", 47 .size = 0x1C0000, 48 .offset = MTDPART_OFS_APPEND, 49 }, { 50 .name = "file system(nor)", 51 .size = MTDPART_SIZ_FULL, 52 .offset = MTDPART_OFS_APPEND, 53 } 54}; 55 56static struct physmap_flash_data ezbrd_flash_data = { 57 .width = 2, 58 .parts = ezbrd_partitions, 59 .nr_parts = ARRAY_SIZE(ezbrd_partitions), 60}; 61 62static struct resource ezbrd_flash_resource = { 63 .start = 0x20000000, 64#if IS_ENABLED(CONFIG_SPI_BFIN5XX) 65 .end = 0x202fffff, 66#else 67 .end = 0x203fffff, 68#endif 69 .flags = IORESOURCE_MEM, 70}; 71 72static struct platform_device ezbrd_flash_device = { 73 .name = "physmap-flash", 74 .id = 0, 75 .dev = { 76 .platform_data = &ezbrd_flash_data, 77 }, 78 .num_resources = 1, 79 .resource = &ezbrd_flash_resource, 80}; 81#endif 82 83#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) 84static struct platform_device rtc_device = { 85 .name = "rtc-bfin", 86 .id = -1, 87}; 88#endif 89 90#if IS_ENABLED(CONFIG_BFIN_MAC) 91#include <linux/bfin_mac.h> 92static const unsigned short bfin_mac_peripherals[] = { 93 P_MII0_ETxD0, 94 P_MII0_ETxD1, 95 P_MII0_ETxEN, 96 P_MII0_ERxD0, 97 P_MII0_ERxD1, 98 P_MII0_TxCLK, 99 P_MII0_PHYINT, 100 P_MII0_CRS, 101 P_MII0_MDC, 102 P_MII0_MDIO, 103 0 104}; 105 106static struct bfin_phydev_platform_data bfin_phydev_data[] = { 107 { 108#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M) 109 .addr = 3, 110#else 111 .addr = 1, 112#endif 113 .irq = IRQ_MAC_PHYINT, 114 }, 115}; 116 117static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { 118 .phydev_number = 1, 119 .phydev_data = bfin_phydev_data, 120 .phy_mode = PHY_INTERFACE_MODE_MII, 121 .mac_peripherals = bfin_mac_peripherals, 122#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M) 123 .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */ 124#endif 125 .vlan1_mask = 1, 126 .vlan2_mask = 2, 127}; 128 129static struct platform_device bfin_mii_bus = { 130 .name = "bfin_mii_bus", 131 .dev = { 132 .platform_data = &bfin_mii_bus_data, 133 } 134}; 135 136static struct platform_device bfin_mac_device = { 137 .name = "bfin_mac", 138 .dev = { 139 .platform_data = &bfin_mii_bus, 140 } 141}; 142 143#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M) 144static struct dsa_chip_data ksz8893m_switch_chip_data = { 145 .mii_bus = &bfin_mii_bus.dev, 146 .port_names = { 147 NULL, 148 "eth%d", 149 "eth%d", 150 "cpu", 151 }, 152}; 153static struct dsa_platform_data ksz8893m_switch_data = { 154 .nr_chips = 1, 155 .netdev = &bfin_mac_device.dev, 156 .chip = &ksz8893m_switch_chip_data, 157}; 158 159static struct platform_device ksz8893m_switch_device = { 160 .name = "dsa", 161 .id = 0, 162 .num_resources = 0, 163 .dev.platform_data = &ksz8893m_switch_data, 164}; 165#endif 166#endif 167 168#if IS_ENABLED(CONFIG_MTD_M25P80) 169static struct mtd_partition bfin_spi_flash_partitions[] = { 170 { 171 .name = "bootloader(spi)", 172 .size = 0x00040000, 173 .offset = 0, 174 .mask_flags = MTD_CAP_ROM 175 }, { 176 .name = "linux kernel(spi)", 177 .size = MTDPART_SIZ_FULL, 178 .offset = MTDPART_OFS_APPEND, 179 } 180}; 181 182static struct flash_platform_data bfin_spi_flash_data = { 183 .name = "m25p80", 184 .parts = bfin_spi_flash_partitions, 185 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), 186 .type = "m25p16", 187}; 188 189/* SPI flash chip (m25p64) */ 190static struct bfin5xx_spi_chip spi_flash_chip_info = { 191 .enable_dma = 0, /* use dma transfer with this chip*/ 192}; 193#endif 194 195#if IS_ENABLED(CONFIG_MMC_SPI) 196static struct bfin5xx_spi_chip mmc_spi_chip_info = { 197 .enable_dma = 0, 198}; 199#endif 200 201#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) 202static const struct ad7877_platform_data bfin_ad7877_ts_info = { 203 .model = 7877, 204 .vref_delay_usecs = 50, /* internal, no capacitor */ 205 .x_plate_ohms = 419, 206 .y_plate_ohms = 486, 207 .pressure_max = 1000, 208 .pressure_min = 0, 209 .stopacq_polarity = 1, 210 .first_conversion_delay = 3, 211 .acquisition_time = 1, 212 .averaging = 1, 213 .pen_down_acc_interval = 1, 214}; 215#endif 216 217static struct spi_board_info bfin_spi_board_info[] __initdata = { 218#if IS_ENABLED(CONFIG_MTD_M25P80) 219 { 220 /* the modalias must be the same as spi device driver name */ 221 .modalias = "m25p80", /* Name of spi_driver for this device */ 222 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 223 .bus_num = 0, /* Framework bus number */ 224 .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */ 225 .platform_data = &bfin_spi_flash_data, 226 .controller_data = &spi_flash_chip_info, 227 .mode = SPI_MODE_3, 228 }, 229#endif 230 231#if IS_ENABLED(CONFIG_BFIN_MAC) 232#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M) 233 { 234 .modalias = "ksz8893m", 235 .max_speed_hz = 5000000, 236 .bus_num = 0, 237 .chip_select = 1, 238 .platform_data = NULL, 239 .mode = SPI_MODE_3, 240 }, 241#endif 242#endif 243 244#if IS_ENABLED(CONFIG_MMC_SPI) 245 { 246 .modalias = "mmc_spi", 247 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 248 .bus_num = 0, 249 .chip_select = 5, 250 .controller_data = &mmc_spi_chip_info, 251 .mode = SPI_MODE_3, 252 }, 253#endif 254#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) 255 { 256 .modalias = "ad7877", 257 .platform_data = &bfin_ad7877_ts_info, 258 .irq = IRQ_PF8, 259 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 260 .bus_num = 0, 261 .chip_select = 2, 262 }, 263#endif 264#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \ 265 && defined(CONFIG_SND_SOC_WM8731_SPI) 266 { 267 .modalias = "wm8731", 268 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 269 .bus_num = 0, 270 .chip_select = 5, 271 .mode = SPI_MODE_0, 272 }, 273#endif 274#if IS_ENABLED(CONFIG_SPI_SPIDEV) 275 { 276 .modalias = "spidev", 277 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 278 .bus_num = 0, 279 .chip_select = 1, 280 }, 281#endif 282#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) 283 { 284 .modalias = "bfin-lq035q1-spi", 285 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 286 .bus_num = 0, 287 .chip_select = 1, 288 .mode = SPI_CPHA | SPI_CPOL, 289 }, 290#endif 291}; 292 293/* SPI controller data */ 294#if IS_ENABLED(CONFIG_SPI_BFIN5XX) 295/* SPI (0) */ 296static struct bfin5xx_spi_master bfin_spi0_info = { 297 .num_chipselect = 6, 298 .enable_dma = 1, /* master has the ability to do dma transfer */ 299 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 300}; 301 302static struct resource bfin_spi0_resource[] = { 303 [0] = { 304 .start = SPI0_REGBASE, 305 .end = SPI0_REGBASE + 0xFF, 306 .flags = IORESOURCE_MEM, 307 }, 308 [1] = { 309 .start = CH_SPI0, 310 .end = CH_SPI0, 311 .flags = IORESOURCE_DMA, 312 }, 313 [2] = { 314 .start = IRQ_SPI0, 315 .end = IRQ_SPI0, 316 .flags = IORESOURCE_IRQ, 317 }, 318}; 319 320static struct platform_device bfin_spi0_device = { 321 .name = "bfin-spi", 322 .id = 0, /* Bus number */ 323 .num_resources = ARRAY_SIZE(bfin_spi0_resource), 324 .resource = bfin_spi0_resource, 325 .dev = { 326 .platform_data = &bfin_spi0_info, /* Passed to driver */ 327 }, 328}; 329 330/* SPI (1) */ 331static struct bfin5xx_spi_master bfin_spi1_info = { 332 .num_chipselect = 6, 333 .enable_dma = 1, /* master has the ability to do dma transfer */ 334 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 335}; 336 337static struct resource bfin_spi1_resource[] = { 338 [0] = { 339 .start = SPI1_REGBASE, 340 .end = SPI1_REGBASE + 0xFF, 341 .flags = IORESOURCE_MEM, 342 }, 343 [1] = { 344 .start = CH_SPI1, 345 .end = CH_SPI1, 346 .flags = IORESOURCE_DMA, 347 }, 348 [2] = { 349 .start = IRQ_SPI1, 350 .end = IRQ_SPI1, 351 .flags = IORESOURCE_IRQ, 352 }, 353}; 354 355static struct platform_device bfin_spi1_device = { 356 .name = "bfin-spi", 357 .id = 1, /* Bus number */ 358 .num_resources = ARRAY_SIZE(bfin_spi1_resource), 359 .resource = bfin_spi1_resource, 360 .dev = { 361 .platform_data = &bfin_spi1_info, /* Passed to driver */ 362 }, 363}; 364#endif /* spi master and devices */ 365 366#if IS_ENABLED(CONFIG_SERIAL_BFIN) 367#ifdef CONFIG_SERIAL_BFIN_UART0 368static struct resource bfin_uart0_resources[] = { 369 { 370 .start = UART0_THR, 371 .end = UART0_GCTL+2, 372 .flags = IORESOURCE_MEM, 373 }, 374 { 375 .start = IRQ_UART0_TX, 376 .end = IRQ_UART0_TX, 377 .flags = IORESOURCE_IRQ, 378 }, 379 { 380 .start = IRQ_UART0_RX, 381 .end = IRQ_UART0_RX, 382 .flags = IORESOURCE_IRQ, 383 }, 384 { 385 .start = IRQ_UART0_ERROR, 386 .end = IRQ_UART0_ERROR, 387 .flags = IORESOURCE_IRQ, 388 }, 389 { 390 .start = CH_UART0_TX, 391 .end = CH_UART0_TX, 392 .flags = IORESOURCE_DMA, 393 }, 394 { 395 .start = CH_UART0_RX, 396 .end = CH_UART0_RX, 397 .flags = IORESOURCE_DMA, 398 }, 399}; 400 401static unsigned short bfin_uart0_peripherals[] = { 402 P_UART0_TX, P_UART0_RX, 0 403}; 404 405static struct platform_device bfin_uart0_device = { 406 .name = "bfin-uart", 407 .id = 0, 408 .num_resources = ARRAY_SIZE(bfin_uart0_resources), 409 .resource = bfin_uart0_resources, 410 .dev = { 411 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ 412 }, 413}; 414#endif 415#ifdef CONFIG_SERIAL_BFIN_UART1 416static struct resource bfin_uart1_resources[] = { 417 { 418 .start = UART1_THR, 419 .end = UART1_GCTL+2, 420 .flags = IORESOURCE_MEM, 421 }, 422 { 423 .start = IRQ_UART1_TX, 424 .end = IRQ_UART1_TX, 425 .flags = IORESOURCE_IRQ, 426 }, 427 { 428 .start = IRQ_UART1_RX, 429 .end = IRQ_UART1_RX, 430 .flags = IORESOURCE_IRQ, 431 }, 432 { 433 .start = IRQ_UART1_ERROR, 434 .end = IRQ_UART1_ERROR, 435 .flags = IORESOURCE_IRQ, 436 }, 437 { 438 .start = CH_UART1_TX, 439 .end = CH_UART1_TX, 440 .flags = IORESOURCE_DMA, 441 }, 442 { 443 .start = CH_UART1_RX, 444 .end = CH_UART1_RX, 445 .flags = IORESOURCE_DMA, 446 }, 447}; 448 449static unsigned short bfin_uart1_peripherals[] = { 450 P_UART1_TX, P_UART1_RX, 0 451}; 452 453static struct platform_device bfin_uart1_device = { 454 .name = "bfin-uart", 455 .id = 1, 456 .num_resources = ARRAY_SIZE(bfin_uart1_resources), 457 .resource = bfin_uart1_resources, 458 .dev = { 459 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ 460 }, 461}; 462#endif 463#endif 464 465#if IS_ENABLED(CONFIG_BFIN_SIR) 466#ifdef CONFIG_BFIN_SIR0 467static struct resource bfin_sir0_resources[] = { 468 { 469 .start = 0xFFC00400, 470 .end = 0xFFC004FF, 471 .flags = IORESOURCE_MEM, 472 }, 473 { 474 .start = IRQ_UART0_RX, 475 .end = IRQ_UART0_RX+1, 476 .flags = IORESOURCE_IRQ, 477 }, 478 { 479 .start = CH_UART0_RX, 480 .end = CH_UART0_RX+1, 481 .flags = IORESOURCE_DMA, 482 }, 483}; 484 485static struct platform_device bfin_sir0_device = { 486 .name = "bfin_sir", 487 .id = 0, 488 .num_resources = ARRAY_SIZE(bfin_sir0_resources), 489 .resource = bfin_sir0_resources, 490}; 491#endif 492#ifdef CONFIG_BFIN_SIR1 493static struct resource bfin_sir1_resources[] = { 494 { 495 .start = 0xFFC02000, 496 .end = 0xFFC020FF, 497 .flags = IORESOURCE_MEM, 498 }, 499 { 500 .start = IRQ_UART1_RX, 501 .end = IRQ_UART1_RX+1, 502 .flags = IORESOURCE_IRQ, 503 }, 504 { 505 .start = CH_UART1_RX, 506 .end = CH_UART1_RX+1, 507 .flags = IORESOURCE_DMA, 508 }, 509}; 510 511static struct platform_device bfin_sir1_device = { 512 .name = "bfin_sir", 513 .id = 1, 514 .num_resources = ARRAY_SIZE(bfin_sir1_resources), 515 .resource = bfin_sir1_resources, 516}; 517#endif 518#endif 519 520#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) 521static struct platform_device bfin_i2s = { 522 .name = "bfin-i2s", 523 .id = CONFIG_SND_BF5XX_SPORT_NUM, 524 /* TODO: add platform data here */ 525}; 526#endif 527 528#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) 529static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; 530 531static struct resource bfin_twi0_resource[] = { 532 [0] = { 533 .start = TWI0_REGBASE, 534 .end = TWI0_REGBASE, 535 .flags = IORESOURCE_MEM, 536 }, 537 [1] = { 538 .start = IRQ_TWI, 539 .end = IRQ_TWI, 540 .flags = IORESOURCE_IRQ, 541 }, 542}; 543 544static struct platform_device i2c_bfin_twi_device = { 545 .name = "i2c-bfin-twi", 546 .id = 0, 547 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 548 .resource = bfin_twi0_resource, 549 .dev = { 550 .platform_data = &bfin_twi0_pins, 551 }, 552}; 553#endif 554 555static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 556#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) 557 { 558 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 559 }, 560#endif 561#if IS_ENABLED(CONFIG_INPUT_PCF8574) 562 { 563 I2C_BOARD_INFO("pcf8574_keypad", 0x27), 564 .irq = IRQ_PF8, 565 }, 566#endif 567#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) 568 { 569 I2C_BOARD_INFO("ssm2602", 0x1b), 570 }, 571#endif 572}; 573 574#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) 575#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 576static struct resource bfin_sport0_uart_resources[] = { 577 { 578 .start = SPORT0_TCR1, 579 .end = SPORT0_MRCS3+4, 580 .flags = IORESOURCE_MEM, 581 }, 582 { 583 .start = IRQ_SPORT0_RX, 584 .end = IRQ_SPORT0_RX+1, 585 .flags = IORESOURCE_IRQ, 586 }, 587 { 588 .start = IRQ_SPORT0_ERROR, 589 .end = IRQ_SPORT0_ERROR, 590 .flags = IORESOURCE_IRQ, 591 }, 592}; 593 594static unsigned short bfin_sport0_peripherals[] = { 595 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 596 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 597}; 598 599static struct platform_device bfin_sport0_uart_device = { 600 .name = "bfin-sport-uart", 601 .id = 0, 602 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), 603 .resource = bfin_sport0_uart_resources, 604 .dev = { 605 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ 606 }, 607}; 608#endif 609#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 610static struct resource bfin_sport1_uart_resources[] = { 611 { 612 .start = SPORT1_TCR1, 613 .end = SPORT1_MRCS3+4, 614 .flags = IORESOURCE_MEM, 615 }, 616 { 617 .start = IRQ_SPORT1_RX, 618 .end = IRQ_SPORT1_RX+1, 619 .flags = IORESOURCE_IRQ, 620 }, 621 { 622 .start = IRQ_SPORT1_ERROR, 623 .end = IRQ_SPORT1_ERROR, 624 .flags = IORESOURCE_IRQ, 625 }, 626}; 627 628static unsigned short bfin_sport1_peripherals[] = { 629 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 630 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 631}; 632 633static struct platform_device bfin_sport1_uart_device = { 634 .name = "bfin-sport-uart", 635 .id = 1, 636 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), 637 .resource = bfin_sport1_uart_resources, 638 .dev = { 639 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ 640 }, 641}; 642#endif 643#endif 644 645#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) 646#include <linux/input.h> 647#include <linux/gpio_keys.h> 648 649static struct gpio_keys_button bfin_gpio_keys_table[] = { 650 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, 651 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, 652}; 653 654static struct gpio_keys_platform_data bfin_gpio_keys_data = { 655 .buttons = bfin_gpio_keys_table, 656 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), 657}; 658 659static struct platform_device bfin_device_gpiokeys = { 660 .name = "gpio-keys", 661 .dev = { 662 .platform_data = &bfin_gpio_keys_data, 663 }, 664}; 665#endif 666 667#if IS_ENABLED(CONFIG_SDH_BFIN) 668 669static struct bfin_sd_host bfin_sdh_data = { 670 .dma_chan = CH_RSI, 671 .irq_int0 = IRQ_RSI_INT0, 672 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0}, 673}; 674 675static struct platform_device bf51x_sdh_device = { 676 .name = "bfin-sdh", 677 .id = 0, 678 .dev = { 679 .platform_data = &bfin_sdh_data, 680 }, 681}; 682#endif 683 684static const unsigned int cclk_vlev_datasheet[] = 685{ 686 VRPAIR(VLEV_100, 400000000), 687 VRPAIR(VLEV_105, 426000000), 688 VRPAIR(VLEV_110, 500000000), 689 VRPAIR(VLEV_115, 533000000), 690 VRPAIR(VLEV_120, 600000000), 691}; 692 693static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 694 .tuple_tab = cclk_vlev_datasheet, 695 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 696 .vr_settling_time = 25 /* us */, 697}; 698 699static struct platform_device bfin_dpmc = { 700 .name = "bfin dpmc", 701 .dev = { 702 .platform_data = &bfin_dmpc_vreg_data, 703 }, 704}; 705 706static struct platform_device *stamp_devices[] __initdata = { 707 708 &bfin_dpmc, 709 710#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) 711 &rtc_device, 712#endif 713 714#if IS_ENABLED(CONFIG_BFIN_MAC) 715 &bfin_mii_bus, 716 &bfin_mac_device, 717#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M) 718 &ksz8893m_switch_device, 719#endif 720#endif 721 722#if IS_ENABLED(CONFIG_SPI_BFIN5XX) 723 &bfin_spi0_device, 724 &bfin_spi1_device, 725#endif 726 727#if IS_ENABLED(CONFIG_SERIAL_BFIN) 728#ifdef CONFIG_SERIAL_BFIN_UART0 729 &bfin_uart0_device, 730#endif 731#ifdef CONFIG_SERIAL_BFIN_UART1 732 &bfin_uart1_device, 733#endif 734#endif 735 736#if IS_ENABLED(CONFIG_BFIN_SIR) 737#ifdef CONFIG_BFIN_SIR0 738 &bfin_sir0_device, 739#endif 740#ifdef CONFIG_BFIN_SIR1 741 &bfin_sir1_device, 742#endif 743#endif 744 745#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) 746 &i2c_bfin_twi_device, 747#endif 748 749#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) 750 &bfin_i2s, 751#endif 752 753#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) 754#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 755 &bfin_sport0_uart_device, 756#endif 757#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 758 &bfin_sport1_uart_device, 759#endif 760#endif 761 762#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) 763 &bfin_device_gpiokeys, 764#endif 765 766#if IS_ENABLED(CONFIG_SDH_BFIN) 767 &bf51x_sdh_device, 768#endif 769 770#if IS_ENABLED(CONFIG_MTD_PHYSMAP) 771 &ezbrd_flash_device, 772#endif 773}; 774 775static int __init ezbrd_init(void) 776{ 777 printk(KERN_INFO "%s(): registering device resources\n", __func__); 778 i2c_register_board_info(0, bfin_i2c_board_info, 779 ARRAY_SIZE(bfin_i2c_board_info)); 780 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); 781 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 782 /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */ 783 peripheral_request(P_AMS2, "ParaFlash"); 784#if !IS_ENABLED(CONFIG_SPI_BFIN5XX) 785 peripheral_request(P_AMS3, "ParaFlash"); 786#endif 787 return 0; 788} 789 790arch_initcall(ezbrd_init); 791 792static struct platform_device *ezbrd_early_devices[] __initdata = { 793#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) 794#ifdef CONFIG_SERIAL_BFIN_UART0 795 &bfin_uart0_device, 796#endif 797#ifdef CONFIG_SERIAL_BFIN_UART1 798 &bfin_uart1_device, 799#endif 800#endif 801 802#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) 803#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 804 &bfin_sport0_uart_device, 805#endif 806#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 807 &bfin_sport1_uart_device, 808#endif 809#endif 810}; 811 812void __init native_machine_early_platform_add_devices(void) 813{ 814 printk(KERN_INFO "register early platform devices\n"); 815 early_platform_add_devices(ezbrd_early_devices, 816 ARRAY_SIZE(ezbrd_early_devices)); 817} 818 819void native_machine_restart(char *cmd) 820{ 821 /* workaround reboot hang when booting from SPI */ 822 if ((bfin_read_SYSCR() & 0x7) == 0x3) 823 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); 824} 825 826int bfin_get_ether_addr(char *addr) 827{ 828 /* the MAC is stored in OTP memory page 0xDF */ 829 u32 ret; 830 u64 otp_mac; 831 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A; 832 833 ret = otp_read(0xDF, 0x00, &otp_mac); 834 if (!(ret & 0x1)) { 835 char *otp_mac_p = (char *)&otp_mac; 836 for (ret = 0; ret < 6; ++ret) 837 addr[ret] = otp_mac_p[5 - ret]; 838 } 839 return 0; 840} 841EXPORT_SYMBOL(bfin_get_ether_addr); 842