1/*
2 * DO NOT EDIT THIS FILE
3 * This file is under version control at
4 *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE
7 *
8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the Clear BSD license.
10 */
11
12/* This file should be up to date with:
13 *  - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
14 */
15
16#if __SILICON_REVISION__ < 0
17# error will not work on BF518 silicon version
18#endif
19
20#ifndef _MACH_ANOMALY_H_
21#define _MACH_ANOMALY_H_
22
23/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
24#define ANOMALY_05000074 (1)
25/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
26#define ANOMALY_05000119 (1)
27/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
28#define ANOMALY_05000122 (1)
29/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
30#define ANOMALY_05000245 (1)
31/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
32#define ANOMALY_05000254 (1)
33/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
34#define ANOMALY_05000265 (1)
35/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
36#define ANOMALY_05000310 (1)
37/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
38#define ANOMALY_05000366 (1)
39/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
40#define ANOMALY_05000405 (1)
41/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
42#define ANOMALY_05000408 (1)
43/* Speculative Fetches Can Cause Undesired External FIFO Operations */
44#define ANOMALY_05000416 (1)
45/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
46#define ANOMALY_05000421 (1)
47/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
48#define ANOMALY_05000422 (1)
49/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
50#define ANOMALY_05000426 (1)
51/* Software System Reset Corrupts PLL_LOCKCNT Register */
52#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
53/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
54#define ANOMALY_05000431 (1)
55/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
56#define ANOMALY_05000434 (1)
57/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
58#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
59/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
60#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
61/* Preboot Cannot be Used to Alter the PLL_DIV Register */
62#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
63/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
64#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
65/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
66#define ANOMALY_05000443 (1)
67/* Incorrect L1 Instruction Bank B Memory Map Location */
68#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
69/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
70#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
71/* PWM_TRIPB Signal Not Available on PG10 */
72#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
73/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
74#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
75/* False Hardware Error when RETI Points to Invalid Memory */
76#define ANOMALY_05000461 (1)
77/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
78#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
79/* Incorrect Default MSEL Value in PLL_CTL */
80#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
81/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
82#define ANOMALY_05000473 (1)
83/* TESTSET Instruction Cannot Be Interrupted */
84#define ANOMALY_05000477 (1)
85/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
86#define ANOMALY_05000481 (1)
87/* PLL Latches Incorrect Settings During Reset */
88#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
89/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
90#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
91/* SPI Master Boot Can Fail Under Certain Conditions */
92#define ANOMALY_05000490 (1)
93/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
94#define ANOMALY_05000491 (1)
95/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
96#define ANOMALY_05000494 (1)
97/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
98#define ANOMALY_05000498 (1)
99/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
100#define ANOMALY_05000501 (1)
101
102/* Anomalies that don't exist on this proc */
103#define ANOMALY_05000099 (0)
104#define ANOMALY_05000120 (0)
105#define ANOMALY_05000125 (0)
106#define ANOMALY_05000149 (0)
107#define ANOMALY_05000158 (0)
108#define ANOMALY_05000171 (0)
109#define ANOMALY_05000179 (0)
110#define ANOMALY_05000182 (0)
111#define ANOMALY_05000183 (0)
112#define ANOMALY_05000189 (0)
113#define ANOMALY_05000198 (0)
114#define ANOMALY_05000202 (0)
115#define ANOMALY_05000215 (0)
116#define ANOMALY_05000219 (0)
117#define ANOMALY_05000220 (0)
118#define ANOMALY_05000227 (0)
119#define ANOMALY_05000230 (0)
120#define ANOMALY_05000231 (0)
121#define ANOMALY_05000233 (0)
122#define ANOMALY_05000234 (0)
123#define ANOMALY_05000242 (0)
124#define ANOMALY_05000244 (0)
125#define ANOMALY_05000248 (0)
126#define ANOMALY_05000250 (0)
127#define ANOMALY_05000257 (0)
128#define ANOMALY_05000261 (0)
129#define ANOMALY_05000263 (0)
130#define ANOMALY_05000266 (0)
131#define ANOMALY_05000273 (0)
132#define ANOMALY_05000274 (0)
133#define ANOMALY_05000278 (0)
134#define ANOMALY_05000281 (0)
135#define ANOMALY_05000283 (0)
136#define ANOMALY_05000285 (0)
137#define ANOMALY_05000287 (0)
138#define ANOMALY_05000301 (0)
139#define ANOMALY_05000305 (0)
140#define ANOMALY_05000307 (0)
141#define ANOMALY_05000311 (0)
142#define ANOMALY_05000312 (0)
143#define ANOMALY_05000315 (0)
144#define ANOMALY_05000323 (0)
145#define ANOMALY_05000353 (0)
146#define ANOMALY_05000357 (0)
147#define ANOMALY_05000362 (1)
148#define ANOMALY_05000363 (0)
149#define ANOMALY_05000364 (0)
150#define ANOMALY_05000371 (0)
151#define ANOMALY_05000380 (0)
152#define ANOMALY_05000383 (0)
153#define ANOMALY_05000386 (0)
154#define ANOMALY_05000389 (0)
155#define ANOMALY_05000400 (0)
156#define ANOMALY_05000402 (0)
157#define ANOMALY_05000412 (0)
158#define ANOMALY_05000432 (0)
159#define ANOMALY_05000447 (0)
160#define ANOMALY_05000448 (0)
161#define ANOMALY_05000456 (0)
162#define ANOMALY_05000450 (0)
163#define ANOMALY_05000465 (0)
164#define ANOMALY_05000467 (0)
165#define ANOMALY_05000474 (0)
166#define ANOMALY_05000475 (0)
167#define ANOMALY_05000480 (0)
168#define ANOMALY_16000030 (0)
169
170#endif
171