1/****************************************************************************/
2
3/*
4 * m52xxacr.h -- ColdFire version 2 core cache support
5 *
6 * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
7 */
8
9/****************************************************************************/
10#ifndef m52xxacr_h
11#define m52xxacr_h
12/****************************************************************************/
13
14/*
15 * All varients of the ColdFire using version 2 cores have a similar
16 * cache setup. Although not absolutely identical the cache register
17 * definitions are compatible for all of them. Mostly they support a
18 * configurable cache memory that can be instruction only, data only,
19 * or split instruction and data. The exception is the very old version 2
20 * core based parts, like the 5206(e), 5249 and 5272, which are instruction
21 * cache only. Cache size varies from 2k up to 16k.
22 */
23
24/*
25 * Define the Cache Control register flags.
26 */
27#define CACR_CENB	0x80000000	/* Enable cache */
28#define CACR_CDPI	0x10000000	/* Disable invalidation by CPUSHL */
29#define CACR_CFRZ	0x08000000	/* Cache freeze mode */
30#define CACR_CINV	0x01000000	/* Invalidate cache */
31#define CACR_DISI	0x00800000	/* Disable instruction cache */
32#define CACR_DISD	0x00400000	/* Disable data cache */
33#define CACR_INVI	0x00200000	/* Invalidate instruction cache */
34#define CACR_INVD	0x00100000	/* Invalidate data cache */
35#define CACR_CEIB	0x00000400	/* Non-cachable instruction burst */
36#define CACR_DCM	0x00000200	/* Default cache mode */
37#define CACR_DBWE	0x00000100	/* Buffered write enable */
38#define CACR_DWP	0x00000020	/* Write protection */
39#define CACR_EUSP	0x00000010	/* Enable separate user a7 */
40
41/*
42 * Define the Access Control register flags.
43 */
44#define ACR_BASE_POS	24		/* Address Base (upper 8 bits) */
45#define ACR_MASK_POS	16		/* Address Mask (next 8 bits) */
46#define ACR_ENABLE	0x00008000	/* Enable this ACR */
47#define ACR_USER	0x00000000	/* Allow only user accesses */
48#define ACR_SUPER	0x00002000	/* Allow supervisor access only */
49#define ACR_ANY		0x00004000	/* Allow any access type */
50#define ACR_CENB	0x00000000	/* Caching of region enabled */
51#define ACR_CDIS	0x00000040	/* Caching of region disabled */
52#define ACR_BWE		0x00000020	/* Write buffer enabled */
53#define ACR_WPROTECT	0x00000004	/* Write protect region */
54
55/*
56 * Set the cache controller settings we will use. On the cores that support
57 * a split cache configuration we allow all the combinations at Kconfig
58 * time. For those cores that only have an instruction cache we just set
59 * that as on.
60 */
61#if defined(CONFIG_CACHE_I)
62#define CACHE_TYPE	(CACR_DISD + CACR_EUSP)
63#define CACHE_INVTYPEI	0
64#elif defined(CONFIG_CACHE_D)
65#define CACHE_TYPE	(CACR_DISI + CACR_EUSP)
66#define CACHE_INVTYPED	0
67#elif defined(CONFIG_CACHE_BOTH)
68#define CACHE_TYPE	CACR_EUSP
69#define CACHE_INVTYPEI	CACR_INVI
70#define CACHE_INVTYPED	CACR_INVD
71#else
72/* This is the instruction cache only devices (no split cache, no eusp) */
73#define CACHE_TYPE	0
74#define CACHE_INVTYPEI	0
75#endif
76
77#define CACHE_INIT	(CACR_CINV + CACHE_TYPE)
78#define CACHE_MODE	(CACR_CENB + CACHE_TYPE + CACR_DCM)
79
80#define CACHE_INVALIDATE  (CACHE_MODE + CACR_CINV)
81#if defined(CACHE_INVTYPEI)
82#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
83#endif
84#if defined(CACHE_INVTYPED)
85#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
86#endif
87
88#define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
89			 (0x000f0000) + \
90			 (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
91#define ACR1_MODE	0
92
93/****************************************************************************/
94#endif  /* m52xxsim_h */
95