1/* 2 * Alchemy clocks. 3 * 4 * Exposes all configurable internal clock sources to the clk framework. 5 * 6 * We have: 7 * - Root source, usually 12MHz supplied by an external crystal 8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2] 9 * 10 * Dividers: 11 * - 6 clock dividers with: 12 * * selectable source [one of the PLLs], 13 * * output divided between [2 .. 512 in steps of 2] (!Au1300) 14 * or [1 .. 256 in steps of 1] (Au1300), 15 * * can be enabled individually. 16 * 17 * - up to 6 "internal" (fixed) consumers which: 18 * * take either AUXPLL or one of the above 6 dividers as input, 19 * * divide this input by 1, 2, or 4 (and 3 on Au1300). 20 * * can be disabled separately. 21 * 22 * Misc clocks: 23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4. 24 * depends on board design and should be set by bootloader, read-only. 25 * - peripheral clock: half the rate of sysbus clock, source for a lot 26 * of peripheral blocks, read-only. 27 * - memory clock: clk rate to main memory chips, depends on board 28 * design and is read-only, 29 * - lrclk: the static bus clock signal for synchronous operation. 30 * depends on board design, must be set by bootloader, 31 * but may be required to correctly configure devices attached to 32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on 33 * later models it's called RCLK. 34 */ 35 36#include <linux/init.h> 37#include <linux/io.h> 38#include <linux/clk-provider.h> 39#include <linux/clkdev.h> 40#include <linux/slab.h> 41#include <linux/spinlock.h> 42#include <linux/types.h> 43#include <asm/mach-au1x00/au1000.h> 44 45/* Base clock: 12MHz is the default in all databooks, and I haven't 46 * found any board yet which uses a different rate. 47 */ 48#define ALCHEMY_ROOTCLK_RATE 12000000 49 50/* 51 * the internal sources which can be driven by the PLLs and dividers. 52 * Names taken from the databooks, refer to them for more information, 53 * especially which ones are share a clock line. 54 */ 55static const char * const alchemy_au1300_intclknames[] = { 56 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk", 57 "EXTCLK0", "EXTCLK1" 58}; 59 60static const char * const alchemy_au1200_intclknames[] = { 61 "lcd_intclk", NULL, NULL, NULL, "EXTCLK0", "EXTCLK1" 62}; 63 64static const char * const alchemy_au1550_intclknames[] = { 65 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko", 66 "EXTCLK0", "EXTCLK1" 67}; 68 69static const char * const alchemy_au1100_intclknames[] = { 70 "usb_clk", "lcd_intclk", NULL, "i2s_clk", "EXTCLK0", "EXTCLK1" 71}; 72 73static const char * const alchemy_au1500_intclknames[] = { 74 NULL, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1" 75}; 76 77static const char * const alchemy_au1000_intclknames[] = { 78 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0", 79 "EXTCLK1" 80}; 81 82/* aliases for a few on-chip sources which are either shared 83 * or have gone through name changes. 84 */ 85static struct clk_aliastable { 86 char *alias; 87 char *base; 88 int cputype; 89} alchemy_clk_aliases[] __initdata = { 90 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100 }, 91 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100 }, 92 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100 }, 93 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550 }, 94 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550 }, 95 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550 }, 96 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550 }, 97 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200 }, 98 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200 }, 99 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 }, 100 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 }, 101 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 }, 102 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 }, 103 104 { NULL, NULL, 0 }, 105}; 106 107#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x)))) 108 109/* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */ 110static spinlock_t alchemy_clk_fg0_lock; 111static spinlock_t alchemy_clk_fg1_lock; 112static spinlock_t alchemy_clk_csrc_lock; 113 114/* CPU Core clock *****************************************************/ 115 116static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw, 117 unsigned long parent_rate) 118{ 119 unsigned long t; 120 121 /* 122 * On early Au1000, sys_cpupll was write-only. Since these 123 * silicon versions of Au1000 are not sold, we don't bend 124 * over backwards trying to determine the frequency. 125 */ 126 if (unlikely(au1xxx_cpu_has_pll_wo())) 127 t = 396000000; 128 else { 129 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f; 130 if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300) 131 t &= 0x3f; 132 t *= parent_rate; 133 } 134 135 return t; 136} 137 138void __init alchemy_set_lpj(void) 139{ 140 preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE); 141 preset_lpj /= 2 * HZ; 142} 143 144static struct clk_ops alchemy_clkops_cpu = { 145 .recalc_rate = alchemy_clk_cpu_recalc, 146}; 147 148static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name, 149 int ctype) 150{ 151 struct clk_init_data id; 152 struct clk_hw *h; 153 154 h = kzalloc(sizeof(*h), GFP_KERNEL); 155 if (!h) 156 return ERR_PTR(-ENOMEM); 157 158 id.name = ALCHEMY_CPU_CLK; 159 id.parent_names = &parent_name; 160 id.num_parents = 1; 161 id.flags = CLK_IS_BASIC; 162 id.ops = &alchemy_clkops_cpu; 163 h->init = &id; 164 165 return clk_register(NULL, h); 166} 167 168/* AUXPLLs ************************************************************/ 169 170struct alchemy_auxpll_clk { 171 struct clk_hw hw; 172 unsigned long reg; /* au1300 has also AUXPLL2 */ 173 int maxmult; /* max multiplier */ 174}; 175#define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw) 176 177static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw, 178 unsigned long parent_rate) 179{ 180 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); 181 182 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate; 183} 184 185static int alchemy_clk_aux_setr(struct clk_hw *hw, 186 unsigned long rate, 187 unsigned long parent_rate) 188{ 189 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); 190 unsigned long d = rate; 191 192 if (rate) 193 d /= parent_rate; 194 else 195 d = 0; 196 197 /* minimum is 84MHz, max is 756-1032 depending on variant */ 198 if (((d < 7) && (d != 0)) || (d > a->maxmult)) 199 return -EINVAL; 200 201 alchemy_wrsys(d, a->reg); 202 return 0; 203} 204 205static long alchemy_clk_aux_roundr(struct clk_hw *hw, 206 unsigned long rate, 207 unsigned long *parent_rate) 208{ 209 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); 210 unsigned long mult; 211 212 if (!rate || !*parent_rate) 213 return 0; 214 215 mult = rate / (*parent_rate); 216 217 if (mult && (mult < 7)) 218 mult = 7; 219 if (mult > a->maxmult) 220 mult = a->maxmult; 221 222 return (*parent_rate) * mult; 223} 224 225static struct clk_ops alchemy_clkops_aux = { 226 .recalc_rate = alchemy_clk_aux_recalc, 227 .set_rate = alchemy_clk_aux_setr, 228 .round_rate = alchemy_clk_aux_roundr, 229}; 230 231static struct clk __init *alchemy_clk_setup_aux(const char *parent_name, 232 char *name, int maxmult, 233 unsigned long reg) 234{ 235 struct clk_init_data id; 236 struct clk *c; 237 struct alchemy_auxpll_clk *a; 238 239 a = kzalloc(sizeof(*a), GFP_KERNEL); 240 if (!a) 241 return ERR_PTR(-ENOMEM); 242 243 id.name = name; 244 id.parent_names = &parent_name; 245 id.num_parents = 1; 246 id.flags = CLK_GET_RATE_NOCACHE; 247 id.ops = &alchemy_clkops_aux; 248 249 a->reg = reg; 250 a->maxmult = maxmult; 251 a->hw.init = &id; 252 253 c = clk_register(NULL, &a->hw); 254 if (!IS_ERR(c)) 255 clk_register_clkdev(c, name, NULL); 256 else 257 kfree(a); 258 259 return c; 260} 261 262/* sysbus_clk *********************************************************/ 263 264static struct clk __init *alchemy_clk_setup_sysbus(const char *pn) 265{ 266 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2; 267 struct clk *c; 268 269 c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK, 270 pn, 0, 1, v); 271 if (!IS_ERR(c)) 272 clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL); 273 return c; 274} 275 276/* Peripheral Clock ***************************************************/ 277 278static struct clk __init *alchemy_clk_setup_periph(const char *pn) 279{ 280 /* Peripheral clock runs at half the rate of sysbus clk */ 281 struct clk *c; 282 283 c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK, 284 pn, 0, 1, 2); 285 if (!IS_ERR(c)) 286 clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL); 287 return c; 288} 289 290/* mem clock **********************************************************/ 291 292static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct) 293{ 294 void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR); 295 unsigned long v; 296 struct clk *c; 297 int div; 298 299 switch (ct) { 300 case ALCHEMY_CPU_AU1550: 301 case ALCHEMY_CPU_AU1200: 302 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB); 303 div = (v & (1 << 15)) ? 1 : 2; 304 break; 305 case ALCHEMY_CPU_AU1300: 306 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB); 307 div = (v & (1 << 31)) ? 1 : 2; 308 break; 309 case ALCHEMY_CPU_AU1000: 310 case ALCHEMY_CPU_AU1500: 311 case ALCHEMY_CPU_AU1100: 312 default: 313 div = 2; 314 break; 315 } 316 317 c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn, 318 0, 1, div); 319 if (!IS_ERR(c)) 320 clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL); 321 return c; 322} 323 324/* lrclk: external synchronous static bus clock ***********************/ 325 326static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t) 327{ 328 /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5, 329 * otherwise lrclk=pclk/4. 330 * All other variants: MEM_STCFG0[15:13] = divisor. 331 * L/RCLK = periph_clk / (divisor + 1) 332 * On Au1000, Au1500, Au1100 it's called LCLK, 333 * on later models it's called RCLK, but it's the same thing. 334 */ 335 struct clk *c; 336 unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0); 337 338 switch (t) { 339 case ALCHEMY_CPU_AU1000: 340 case ALCHEMY_CPU_AU1500: 341 v = 4 + ((v >> 11) & 1); 342 break; 343 default: /* all other models */ 344 v = ((v >> 13) & 7) + 1; 345 } 346 c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK, 347 pn, 0, 1, v); 348 if (!IS_ERR(c)) 349 clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL); 350 return c; 351} 352 353/* Clock dividers and muxes *******************************************/ 354 355/* data for fgen and csrc mux-dividers */ 356struct alchemy_fgcs_clk { 357 struct clk_hw hw; 358 spinlock_t *reglock; /* register lock */ 359 unsigned long reg; /* SYS_FREQCTRL0/1 */ 360 int shift; /* offset in register */ 361 int parent; /* parent before disable [Au1300] */ 362 int isen; /* is it enabled? */ 363 int *dt; /* dividertable for csrc */ 364}; 365#define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw) 366 367static long alchemy_calc_div(unsigned long rate, unsigned long prate, 368 int scale, int maxdiv, unsigned long *rv) 369{ 370 long div1, div2; 371 372 div1 = prate / rate; 373 if ((prate / div1) > rate) 374 div1++; 375 376 if (scale == 2) { /* only div-by-multiple-of-2 possible */ 377 if (div1 & 1) 378 div1++; /* stay <=prate */ 379 } 380 381 div2 = (div1 / scale) - 1; /* value to write to register */ 382 383 if (div2 > maxdiv) 384 div2 = maxdiv; 385 if (rv) 386 *rv = div2; 387 388 div1 = ((div2 + 1) * scale); 389 return div1; 390} 391 392static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate, 393 unsigned long *best_parent_rate, 394 struct clk_hw **best_parent_clk, 395 int scale, int maxdiv) 396{ 397 struct clk *pc, *bpc, *free; 398 long tdv, tpr, pr, nr, br, bpr, diff, lastdiff; 399 int j; 400 401 lastdiff = INT_MAX; 402 bpr = 0; 403 bpc = NULL; 404 br = -EINVAL; 405 free = NULL; 406 407 /* look at the rates each enabled parent supplies and select 408 * the one that gets closest to but not over the requested rate. 409 */ 410 for (j = 0; j < 7; j++) { 411 pc = clk_get_parent_by_index(hw->clk, j); 412 if (!pc) 413 break; 414 415 /* if this parent is currently unused, remember it. 416 * XXX: we would actually want clk_has_active_children() 417 * but this is a good-enough approximation for now. 418 */ 419 if (!__clk_is_prepared(pc)) { 420 if (!free) 421 free = pc; 422 } 423 424 pr = clk_get_rate(pc); 425 if (pr < rate) 426 continue; 427 428 /* what can hardware actually provide */ 429 tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL); 430 nr = pr / tdv; 431 diff = rate - nr; 432 if (nr > rate) 433 continue; 434 435 if (diff < lastdiff) { 436 lastdiff = diff; 437 bpr = pr; 438 bpc = pc; 439 br = nr; 440 } 441 if (diff == 0) 442 break; 443 } 444 445 /* if we couldn't get the exact rate we wanted from the enabled 446 * parents, maybe we can tell an available disabled/inactive one 447 * to give us a rate we can divide down to the requested rate. 448 */ 449 if (lastdiff && free) { 450 for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) { 451 tpr = rate * j; 452 if (tpr < 0) 453 break; 454 pr = clk_round_rate(free, tpr); 455 456 tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL); 457 nr = pr / tdv; 458 diff = rate - nr; 459 if (nr > rate) 460 continue; 461 if (diff < lastdiff) { 462 lastdiff = diff; 463 bpr = pr; 464 bpc = free; 465 br = nr; 466 } 467 if (diff == 0) 468 break; 469 } 470 } 471 472 *best_parent_rate = bpr; 473 *best_parent_clk = __clk_get_hw(bpc); 474 return br; 475} 476 477static int alchemy_clk_fgv1_en(struct clk_hw *hw) 478{ 479 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 480 unsigned long v, flags; 481 482 spin_lock_irqsave(c->reglock, flags); 483 v = alchemy_rdsys(c->reg); 484 v |= (1 << 1) << c->shift; 485 alchemy_wrsys(v, c->reg); 486 spin_unlock_irqrestore(c->reglock, flags); 487 488 return 0; 489} 490 491static int alchemy_clk_fgv1_isen(struct clk_hw *hw) 492{ 493 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 494 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1); 495 496 return v & 1; 497} 498 499static void alchemy_clk_fgv1_dis(struct clk_hw *hw) 500{ 501 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 502 unsigned long v, flags; 503 504 spin_lock_irqsave(c->reglock, flags); 505 v = alchemy_rdsys(c->reg); 506 v &= ~((1 << 1) << c->shift); 507 alchemy_wrsys(v, c->reg); 508 spin_unlock_irqrestore(c->reglock, flags); 509} 510 511static int alchemy_clk_fgv1_setp(struct clk_hw *hw, u8 index) 512{ 513 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 514 unsigned long v, flags; 515 516 spin_lock_irqsave(c->reglock, flags); 517 v = alchemy_rdsys(c->reg); 518 if (index) 519 v |= (1 << c->shift); 520 else 521 v &= ~(1 << c->shift); 522 alchemy_wrsys(v, c->reg); 523 spin_unlock_irqrestore(c->reglock, flags); 524 525 return 0; 526} 527 528static u8 alchemy_clk_fgv1_getp(struct clk_hw *hw) 529{ 530 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 531 532 return (alchemy_rdsys(c->reg) >> c->shift) & 1; 533} 534 535static int alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate, 536 unsigned long parent_rate) 537{ 538 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 539 unsigned long div, v, flags, ret; 540 int sh = c->shift + 2; 541 542 if (!rate || !parent_rate || rate > (parent_rate / 2)) 543 return -EINVAL; 544 ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div); 545 spin_lock_irqsave(c->reglock, flags); 546 v = alchemy_rdsys(c->reg); 547 v &= ~(0xff << sh); 548 v |= div << sh; 549 alchemy_wrsys(v, c->reg); 550 spin_unlock_irqrestore(c->reglock, flags); 551 552 return 0; 553} 554 555static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw, 556 unsigned long parent_rate) 557{ 558 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 559 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2); 560 561 v = ((v & 0xff) + 1) * 2; 562 return parent_rate / v; 563} 564 565static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate, 566 unsigned long min_rate, 567 unsigned long max_rate, 568 unsigned long *best_parent_rate, 569 struct clk_hw **best_parent_clk) 570{ 571 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate, 572 best_parent_clk, 2, 512); 573} 574 575/* Au1000, Au1100, Au15x0, Au12x0 */ 576static struct clk_ops alchemy_clkops_fgenv1 = { 577 .recalc_rate = alchemy_clk_fgv1_recalc, 578 .determine_rate = alchemy_clk_fgv1_detr, 579 .set_rate = alchemy_clk_fgv1_setr, 580 .set_parent = alchemy_clk_fgv1_setp, 581 .get_parent = alchemy_clk_fgv1_getp, 582 .enable = alchemy_clk_fgv1_en, 583 .disable = alchemy_clk_fgv1_dis, 584 .is_enabled = alchemy_clk_fgv1_isen, 585}; 586 587static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c) 588{ 589 unsigned long v = alchemy_rdsys(c->reg); 590 591 v &= ~(3 << c->shift); 592 v |= (c->parent & 3) << c->shift; 593 alchemy_wrsys(v, c->reg); 594 c->isen = 1; 595} 596 597static int alchemy_clk_fgv2_en(struct clk_hw *hw) 598{ 599 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 600 unsigned long flags; 601 602 /* enable by setting the previous parent clock */ 603 spin_lock_irqsave(c->reglock, flags); 604 __alchemy_clk_fgv2_en(c); 605 spin_unlock_irqrestore(c->reglock, flags); 606 607 return 0; 608} 609 610static int alchemy_clk_fgv2_isen(struct clk_hw *hw) 611{ 612 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 613 614 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0; 615} 616 617static void alchemy_clk_fgv2_dis(struct clk_hw *hw) 618{ 619 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 620 unsigned long v, flags; 621 622 spin_lock_irqsave(c->reglock, flags); 623 v = alchemy_rdsys(c->reg); 624 v &= ~(3 << c->shift); /* set input mux to "disabled" state */ 625 alchemy_wrsys(v, c->reg); 626 c->isen = 0; 627 spin_unlock_irqrestore(c->reglock, flags); 628} 629 630static int alchemy_clk_fgv2_setp(struct clk_hw *hw, u8 index) 631{ 632 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 633 unsigned long flags; 634 635 spin_lock_irqsave(c->reglock, flags); 636 c->parent = index + 1; /* value to write to register */ 637 if (c->isen) 638 __alchemy_clk_fgv2_en(c); 639 spin_unlock_irqrestore(c->reglock, flags); 640 641 return 0; 642} 643 644static u8 alchemy_clk_fgv2_getp(struct clk_hw *hw) 645{ 646 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 647 unsigned long flags, v; 648 649 spin_lock_irqsave(c->reglock, flags); 650 v = c->parent - 1; 651 spin_unlock_irqrestore(c->reglock, flags); 652 return v; 653} 654 655/* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the 656 * dividers behave exactly as on previous models (dividers are multiples 657 * of 2); with the bit set, dividers are multiples of 1, halving their 658 * range, but making them also much more flexible. 659 */ 660static int alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate, 661 unsigned long parent_rate) 662{ 663 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 664 int sh = c->shift + 2; 665 unsigned long div, v, flags, ret; 666 667 if (!rate || !parent_rate || rate > parent_rate) 668 return -EINVAL; 669 670 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */ 671 ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2, 672 v ? 256 : 512, &div); 673 674 spin_lock_irqsave(c->reglock, flags); 675 v = alchemy_rdsys(c->reg); 676 v &= ~(0xff << sh); 677 v |= (div & 0xff) << sh; 678 alchemy_wrsys(v, c->reg); 679 spin_unlock_irqrestore(c->reglock, flags); 680 681 return 0; 682} 683 684static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw, 685 unsigned long parent_rate) 686{ 687 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 688 int sh = c->shift + 2; 689 unsigned long v, t; 690 691 v = alchemy_rdsys(c->reg); 692 t = parent_rate / (((v >> sh) & 0xff) + 1); 693 if ((v & (1 << 30)) == 0) /* test scale bit */ 694 t /= 2; 695 696 return t; 697} 698 699static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate, 700 unsigned long min_rate, 701 unsigned long max_rate, 702 unsigned long *best_parent_rate, 703 struct clk_hw **best_parent_clk) 704{ 705 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 706 int scale, maxdiv; 707 708 if (alchemy_rdsys(c->reg) & (1 << 30)) { 709 scale = 1; 710 maxdiv = 256; 711 } else { 712 scale = 2; 713 maxdiv = 512; 714 } 715 716 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate, 717 best_parent_clk, scale, maxdiv); 718} 719 720/* Au1300 larger input mux, no separate disable bit, flexible divider */ 721static struct clk_ops alchemy_clkops_fgenv2 = { 722 .recalc_rate = alchemy_clk_fgv2_recalc, 723 .determine_rate = alchemy_clk_fgv2_detr, 724 .set_rate = alchemy_clk_fgv2_setr, 725 .set_parent = alchemy_clk_fgv2_setp, 726 .get_parent = alchemy_clk_fgv2_getp, 727 .enable = alchemy_clk_fgv2_en, 728 .disable = alchemy_clk_fgv2_dis, 729 .is_enabled = alchemy_clk_fgv2_isen, 730}; 731 732static const char * const alchemy_clk_fgv1_parents[] = { 733 ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK 734}; 735 736static const char * const alchemy_clk_fgv2_parents[] = { 737 ALCHEMY_AUXPLL2_CLK, ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK 738}; 739 740static const char * const alchemy_clk_fgen_names[] = { 741 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK, 742 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK }; 743 744static int __init alchemy_clk_init_fgens(int ctype) 745{ 746 struct clk *c; 747 struct clk_init_data id; 748 struct alchemy_fgcs_clk *a; 749 unsigned long v; 750 int i, ret; 751 752 switch (ctype) { 753 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: 754 id.ops = &alchemy_clkops_fgenv1; 755 id.parent_names = (const char **)alchemy_clk_fgv1_parents; 756 id.num_parents = 2; 757 break; 758 case ALCHEMY_CPU_AU1300: 759 id.ops = &alchemy_clkops_fgenv2; 760 id.parent_names = (const char **)alchemy_clk_fgv2_parents; 761 id.num_parents = 3; 762 break; 763 default: 764 return -ENODEV; 765 } 766 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; 767 768 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL); 769 if (!a) 770 return -ENOMEM; 771 772 spin_lock_init(&alchemy_clk_fg0_lock); 773 spin_lock_init(&alchemy_clk_fg1_lock); 774 ret = 0; 775 for (i = 0; i < 6; i++) { 776 id.name = alchemy_clk_fgen_names[i]; 777 a->shift = 10 * (i < 3 ? i : i - 3); 778 if (i > 2) { 779 a->reg = AU1000_SYS_FREQCTRL1; 780 a->reglock = &alchemy_clk_fg1_lock; 781 } else { 782 a->reg = AU1000_SYS_FREQCTRL0; 783 a->reglock = &alchemy_clk_fg0_lock; 784 } 785 786 /* default to first parent if bootloader has set 787 * the mux to disabled state. 788 */ 789 if (ctype == ALCHEMY_CPU_AU1300) { 790 v = alchemy_rdsys(a->reg); 791 a->parent = (v >> a->shift) & 3; 792 if (!a->parent) { 793 a->parent = 1; 794 a->isen = 0; 795 } else 796 a->isen = 1; 797 } 798 799 a->hw.init = &id; 800 c = clk_register(NULL, &a->hw); 801 if (IS_ERR(c)) 802 ret++; 803 else 804 clk_register_clkdev(c, id.name, NULL); 805 a++; 806 } 807 808 return ret; 809} 810 811/* internal sources muxes *********************************************/ 812 813static int alchemy_clk_csrc_isen(struct clk_hw *hw) 814{ 815 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 816 unsigned long v = alchemy_rdsys(c->reg); 817 818 return (((v >> c->shift) >> 2) & 7) != 0; 819} 820 821static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c) 822{ 823 unsigned long v = alchemy_rdsys(c->reg); 824 825 v &= ~((7 << 2) << c->shift); 826 v |= ((c->parent & 7) << 2) << c->shift; 827 alchemy_wrsys(v, c->reg); 828 c->isen = 1; 829} 830 831static int alchemy_clk_csrc_en(struct clk_hw *hw) 832{ 833 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 834 unsigned long flags; 835 836 /* enable by setting the previous parent clock */ 837 spin_lock_irqsave(c->reglock, flags); 838 __alchemy_clk_csrc_en(c); 839 spin_unlock_irqrestore(c->reglock, flags); 840 841 return 0; 842} 843 844static void alchemy_clk_csrc_dis(struct clk_hw *hw) 845{ 846 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 847 unsigned long v, flags; 848 849 spin_lock_irqsave(c->reglock, flags); 850 v = alchemy_rdsys(c->reg); 851 v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */ 852 alchemy_wrsys(v, c->reg); 853 c->isen = 0; 854 spin_unlock_irqrestore(c->reglock, flags); 855} 856 857static int alchemy_clk_csrc_setp(struct clk_hw *hw, u8 index) 858{ 859 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 860 unsigned long flags; 861 862 spin_lock_irqsave(c->reglock, flags); 863 c->parent = index + 1; /* value to write to register */ 864 if (c->isen) 865 __alchemy_clk_csrc_en(c); 866 spin_unlock_irqrestore(c->reglock, flags); 867 868 return 0; 869} 870 871static u8 alchemy_clk_csrc_getp(struct clk_hw *hw) 872{ 873 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 874 875 return c->parent - 1; 876} 877 878static unsigned long alchemy_clk_csrc_recalc(struct clk_hw *hw, 879 unsigned long parent_rate) 880{ 881 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 882 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3; 883 884 return parent_rate / c->dt[v]; 885} 886 887static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate, 888 unsigned long parent_rate) 889{ 890 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 891 unsigned long d, v, flags; 892 int i; 893 894 if (!rate || !parent_rate || rate > parent_rate) 895 return -EINVAL; 896 897 d = (parent_rate + (rate / 2)) / rate; 898 if (d > 4) 899 return -EINVAL; 900 if ((d == 3) && (c->dt[2] != 3)) 901 d = 4; 902 903 for (i = 0; i < 4; i++) 904 if (c->dt[i] == d) 905 break; 906 907 if (i >= 4) 908 return -EINVAL; /* oops */ 909 910 spin_lock_irqsave(c->reglock, flags); 911 v = alchemy_rdsys(c->reg); 912 v &= ~(3 << c->shift); 913 v |= (i & 3) << c->shift; 914 alchemy_wrsys(v, c->reg); 915 spin_unlock_irqrestore(c->reglock, flags); 916 917 return 0; 918} 919 920static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate, 921 unsigned long min_rate, 922 unsigned long max_rate, 923 unsigned long *best_parent_rate, 924 struct clk_hw **best_parent_clk) 925{ 926 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); 927 int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */ 928 929 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate, 930 best_parent_clk, scale, 4); 931} 932 933static struct clk_ops alchemy_clkops_csrc = { 934 .recalc_rate = alchemy_clk_csrc_recalc, 935 .determine_rate = alchemy_clk_csrc_detr, 936 .set_rate = alchemy_clk_csrc_setr, 937 .set_parent = alchemy_clk_csrc_setp, 938 .get_parent = alchemy_clk_csrc_getp, 939 .enable = alchemy_clk_csrc_en, 940 .disable = alchemy_clk_csrc_dis, 941 .is_enabled = alchemy_clk_csrc_isen, 942}; 943 944static const char * const alchemy_clk_csrc_parents[] = { 945 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK, 946 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK, 947 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK 948}; 949 950/* divider tables */ 951static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 }; /* rest */ 952static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */ 953 954static int __init alchemy_clk_setup_imux(int ctype) 955{ 956 struct alchemy_fgcs_clk *a; 957 const char * const *names; 958 struct clk_init_data id; 959 unsigned long v; 960 int i, ret, *dt; 961 struct clk *c; 962 963 id.ops = &alchemy_clkops_csrc; 964 id.parent_names = (const char **)alchemy_clk_csrc_parents; 965 id.num_parents = 7; 966 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; 967 968 dt = alchemy_csrc_dt1; 969 switch (ctype) { 970 case ALCHEMY_CPU_AU1000: 971 names = alchemy_au1000_intclknames; 972 break; 973 case ALCHEMY_CPU_AU1500: 974 names = alchemy_au1500_intclknames; 975 break; 976 case ALCHEMY_CPU_AU1100: 977 names = alchemy_au1100_intclknames; 978 break; 979 case ALCHEMY_CPU_AU1550: 980 names = alchemy_au1550_intclknames; 981 break; 982 case ALCHEMY_CPU_AU1200: 983 names = alchemy_au1200_intclknames; 984 break; 985 case ALCHEMY_CPU_AU1300: 986 dt = alchemy_csrc_dt2; 987 names = alchemy_au1300_intclknames; 988 break; 989 default: 990 return -ENODEV; 991 } 992 993 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL); 994 if (!a) 995 return -ENOMEM; 996 997 spin_lock_init(&alchemy_clk_csrc_lock); 998 ret = 0; 999 1000 for (i = 0; i < 6; i++) { 1001 id.name = names[i]; 1002 if (!id.name) 1003 goto next; 1004 1005 a->shift = i * 5; 1006 a->reg = AU1000_SYS_CLKSRC; 1007 a->reglock = &alchemy_clk_csrc_lock; 1008 a->dt = dt; 1009 1010 /* default to first parent clock if mux is initially 1011 * set to disabled state. 1012 */ 1013 v = alchemy_rdsys(a->reg); 1014 a->parent = ((v >> a->shift) >> 2) & 7; 1015 if (!a->parent) { 1016 a->parent = 1; 1017 a->isen = 0; 1018 } else 1019 a->isen = 1; 1020 1021 a->hw.init = &id; 1022 c = clk_register(NULL, &a->hw); 1023 if (IS_ERR(c)) 1024 ret++; 1025 else 1026 clk_register_clkdev(c, id.name, NULL); 1027next: 1028 a++; 1029 } 1030 1031 return ret; 1032} 1033 1034 1035/**********************************************************************/ 1036 1037 1038#define ERRCK(x) \ 1039 if (IS_ERR(x)) { \ 1040 ret = PTR_ERR(x); \ 1041 goto out; \ 1042 } 1043 1044static int __init alchemy_clk_init(void) 1045{ 1046 int ctype = alchemy_get_cputype(), ret, i; 1047 struct clk_aliastable *t = alchemy_clk_aliases; 1048 struct clk *c; 1049 1050 /* Root of the Alchemy clock tree: external 12MHz crystal osc */ 1051 c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL, 1052 CLK_IS_ROOT, 1053 ALCHEMY_ROOTCLK_RATE); 1054 ERRCK(c) 1055 1056 /* CPU core clock */ 1057 c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype); 1058 ERRCK(c) 1059 1060 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */ 1061 i = (ctype == ALCHEMY_CPU_AU1300) ? 84 : 63; 1062 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK, 1063 i, AU1000_SYS_AUXPLL); 1064 ERRCK(c) 1065 1066 if (ctype == ALCHEMY_CPU_AU1300) { 1067 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, 1068 ALCHEMY_AUXPLL2_CLK, i, 1069 AU1300_SYS_AUXPLL2); 1070 ERRCK(c) 1071 } 1072 1073 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */ 1074 c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK); 1075 ERRCK(c) 1076 1077 /* peripheral clock: runs at half rate of sysbus clk */ 1078 c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK); 1079 ERRCK(c) 1080 1081 /* SDR/DDR memory clock */ 1082 c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype); 1083 ERRCK(c) 1084 1085 /* L/RCLK: external static bus clock for synchronous mode */ 1086 c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype); 1087 ERRCK(c) 1088 1089 /* Frequency dividers 0-5 */ 1090 ret = alchemy_clk_init_fgens(ctype); 1091 if (ret) { 1092 ret = -ENODEV; 1093 goto out; 1094 } 1095 1096 /* diving muxes for internal sources */ 1097 ret = alchemy_clk_setup_imux(ctype); 1098 if (ret) { 1099 ret = -ENODEV; 1100 goto out; 1101 } 1102 1103 /* set up aliases drivers might look for */ 1104 while (t->base) { 1105 if (t->cputype == ctype) 1106 clk_add_alias(t->alias, NULL, t->base, NULL); 1107 t++; 1108 } 1109 1110 pr_info("Alchemy clocktree installed\n"); 1111 return 0; 1112 1113out: 1114 return ret; 1115} 1116postcore_initcall(alchemy_clk_init); 1117