1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_SLI_DEFS_H__ 29#define __CVMX_SLI_DEFS_H__ 30 31#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull) 32#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16) 33#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull) 34#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull) 35#define CVMX_SLI_DBG_DATA (0x0000000000000310ull) 36#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull) 37#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16) 38#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16) 39#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16) 40#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull) 41#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16) 42#define CVMX_SLI_INT_SUM (0x0000000000000330ull) 43#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull) 44#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull) 45#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull) 46#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull) 47#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull) 48#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull) 49#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull) 50#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull) 51#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12) 52#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull) 53#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull) 54#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull) 55#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull) 56#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull) 57#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull) 58#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull) 59#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull) 60#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull) 61#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull) 62#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull) 63#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull) 64#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull) 65#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull) 66#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull) 67#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull) 68#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull) 69#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull) 70#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull) 71#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) 72#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) 73#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) 74#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) 75#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) 76#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) 77#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) 78#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) 79#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) 80#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16) 81#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) 82#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) 83#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) 84#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull) 85#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull) 86#define CVMX_SLI_PKT_CTL (0x0000000000001220ull) 87#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull) 88#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull) 89#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull) 90#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull) 91#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull) 92#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull) 93#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull) 94#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull) 95#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull) 96#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull) 97#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) 98#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull) 99#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull) 100#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull) 101#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull) 102#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull) 103#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull) 104#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull) 105#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull) 106#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull) 107#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull) 108#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull) 109#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull) 110#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull) 111#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull) 112#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16) 113#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16) 114#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull) 115#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull) 116#define CVMX_SLI_STATE1 (0x0000000000000620ull) 117#define CVMX_SLI_STATE2 (0x0000000000000630ull) 118#define CVMX_SLI_STATE3 (0x0000000000000640ull) 119#define CVMX_SLI_TX_PIPE (0x0000000000001230ull) 120#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull) 121#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull) 122#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull) 123#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull) 124#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull) 125#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull) 126 127union cvmx_sli_bist_status { 128 uint64_t u64; 129 struct cvmx_sli_bist_status_s { 130#ifdef __BIG_ENDIAN_BITFIELD 131 uint64_t reserved_32_63:32; 132 uint64_t ncb_req:1; 133 uint64_t n2p0_c:1; 134 uint64_t n2p0_o:1; 135 uint64_t n2p1_c:1; 136 uint64_t n2p1_o:1; 137 uint64_t cpl_p0:1; 138 uint64_t cpl_p1:1; 139 uint64_t reserved_19_24:6; 140 uint64_t p2n0_c0:1; 141 uint64_t p2n0_c1:1; 142 uint64_t p2n0_n:1; 143 uint64_t p2n0_p0:1; 144 uint64_t p2n0_p1:1; 145 uint64_t p2n1_c0:1; 146 uint64_t p2n1_c1:1; 147 uint64_t p2n1_n:1; 148 uint64_t p2n1_p0:1; 149 uint64_t p2n1_p1:1; 150 uint64_t reserved_6_8:3; 151 uint64_t dsi1_1:1; 152 uint64_t dsi1_0:1; 153 uint64_t dsi0_1:1; 154 uint64_t dsi0_0:1; 155 uint64_t msi:1; 156 uint64_t ncb_cmd:1; 157#else 158 uint64_t ncb_cmd:1; 159 uint64_t msi:1; 160 uint64_t dsi0_0:1; 161 uint64_t dsi0_1:1; 162 uint64_t dsi1_0:1; 163 uint64_t dsi1_1:1; 164 uint64_t reserved_6_8:3; 165 uint64_t p2n1_p1:1; 166 uint64_t p2n1_p0:1; 167 uint64_t p2n1_n:1; 168 uint64_t p2n1_c1:1; 169 uint64_t p2n1_c0:1; 170 uint64_t p2n0_p1:1; 171 uint64_t p2n0_p0:1; 172 uint64_t p2n0_n:1; 173 uint64_t p2n0_c1:1; 174 uint64_t p2n0_c0:1; 175 uint64_t reserved_19_24:6; 176 uint64_t cpl_p1:1; 177 uint64_t cpl_p0:1; 178 uint64_t n2p1_o:1; 179 uint64_t n2p1_c:1; 180 uint64_t n2p0_o:1; 181 uint64_t n2p0_c:1; 182 uint64_t ncb_req:1; 183 uint64_t reserved_32_63:32; 184#endif 185 } s; 186 struct cvmx_sli_bist_status_cn61xx { 187#ifdef __BIG_ENDIAN_BITFIELD 188 uint64_t reserved_31_63:33; 189 uint64_t n2p0_c:1; 190 uint64_t n2p0_o:1; 191 uint64_t reserved_27_28:2; 192 uint64_t cpl_p0:1; 193 uint64_t cpl_p1:1; 194 uint64_t reserved_19_24:6; 195 uint64_t p2n0_c0:1; 196 uint64_t p2n0_c1:1; 197 uint64_t p2n0_n:1; 198 uint64_t p2n0_p0:1; 199 uint64_t p2n0_p1:1; 200 uint64_t p2n1_c0:1; 201 uint64_t p2n1_c1:1; 202 uint64_t p2n1_n:1; 203 uint64_t p2n1_p0:1; 204 uint64_t p2n1_p1:1; 205 uint64_t reserved_6_8:3; 206 uint64_t dsi1_1:1; 207 uint64_t dsi1_0:1; 208 uint64_t dsi0_1:1; 209 uint64_t dsi0_0:1; 210 uint64_t msi:1; 211 uint64_t ncb_cmd:1; 212#else 213 uint64_t ncb_cmd:1; 214 uint64_t msi:1; 215 uint64_t dsi0_0:1; 216 uint64_t dsi0_1:1; 217 uint64_t dsi1_0:1; 218 uint64_t dsi1_1:1; 219 uint64_t reserved_6_8:3; 220 uint64_t p2n1_p1:1; 221 uint64_t p2n1_p0:1; 222 uint64_t p2n1_n:1; 223 uint64_t p2n1_c1:1; 224 uint64_t p2n1_c0:1; 225 uint64_t p2n0_p1:1; 226 uint64_t p2n0_p0:1; 227 uint64_t p2n0_n:1; 228 uint64_t p2n0_c1:1; 229 uint64_t p2n0_c0:1; 230 uint64_t reserved_19_24:6; 231 uint64_t cpl_p1:1; 232 uint64_t cpl_p0:1; 233 uint64_t reserved_27_28:2; 234 uint64_t n2p0_o:1; 235 uint64_t n2p0_c:1; 236 uint64_t reserved_31_63:33; 237#endif 238 } cn61xx; 239 struct cvmx_sli_bist_status_cn63xx { 240#ifdef __BIG_ENDIAN_BITFIELD 241 uint64_t reserved_31_63:33; 242 uint64_t n2p0_c:1; 243 uint64_t n2p0_o:1; 244 uint64_t n2p1_c:1; 245 uint64_t n2p1_o:1; 246 uint64_t cpl_p0:1; 247 uint64_t cpl_p1:1; 248 uint64_t reserved_19_24:6; 249 uint64_t p2n0_c0:1; 250 uint64_t p2n0_c1:1; 251 uint64_t p2n0_n:1; 252 uint64_t p2n0_p0:1; 253 uint64_t p2n0_p1:1; 254 uint64_t p2n1_c0:1; 255 uint64_t p2n1_c1:1; 256 uint64_t p2n1_n:1; 257 uint64_t p2n1_p0:1; 258 uint64_t p2n1_p1:1; 259 uint64_t reserved_6_8:3; 260 uint64_t dsi1_1:1; 261 uint64_t dsi1_0:1; 262 uint64_t dsi0_1:1; 263 uint64_t dsi0_0:1; 264 uint64_t msi:1; 265 uint64_t ncb_cmd:1; 266#else 267 uint64_t ncb_cmd:1; 268 uint64_t msi:1; 269 uint64_t dsi0_0:1; 270 uint64_t dsi0_1:1; 271 uint64_t dsi1_0:1; 272 uint64_t dsi1_1:1; 273 uint64_t reserved_6_8:3; 274 uint64_t p2n1_p1:1; 275 uint64_t p2n1_p0:1; 276 uint64_t p2n1_n:1; 277 uint64_t p2n1_c1:1; 278 uint64_t p2n1_c0:1; 279 uint64_t p2n0_p1:1; 280 uint64_t p2n0_p0:1; 281 uint64_t p2n0_n:1; 282 uint64_t p2n0_c1:1; 283 uint64_t p2n0_c0:1; 284 uint64_t reserved_19_24:6; 285 uint64_t cpl_p1:1; 286 uint64_t cpl_p0:1; 287 uint64_t n2p1_o:1; 288 uint64_t n2p1_c:1; 289 uint64_t n2p0_o:1; 290 uint64_t n2p0_c:1; 291 uint64_t reserved_31_63:33; 292#endif 293 } cn63xx; 294 struct cvmx_sli_bist_status_cn63xx cn63xxp1; 295 struct cvmx_sli_bist_status_cn61xx cn66xx; 296 struct cvmx_sli_bist_status_s cn68xx; 297 struct cvmx_sli_bist_status_s cn68xxp1; 298 struct cvmx_sli_bist_status_cn61xx cnf71xx; 299}; 300 301union cvmx_sli_ctl_portx { 302 uint64_t u64; 303 struct cvmx_sli_ctl_portx_s { 304#ifdef __BIG_ENDIAN_BITFIELD 305 uint64_t reserved_22_63:42; 306 uint64_t intd:1; 307 uint64_t intc:1; 308 uint64_t intb:1; 309 uint64_t inta:1; 310 uint64_t dis_port:1; 311 uint64_t waitl_com:1; 312 uint64_t intd_map:2; 313 uint64_t intc_map:2; 314 uint64_t intb_map:2; 315 uint64_t inta_map:2; 316 uint64_t ctlp_ro:1; 317 uint64_t reserved_6_6:1; 318 uint64_t ptlp_ro:1; 319 uint64_t reserved_1_4:4; 320 uint64_t wait_com:1; 321#else 322 uint64_t wait_com:1; 323 uint64_t reserved_1_4:4; 324 uint64_t ptlp_ro:1; 325 uint64_t reserved_6_6:1; 326 uint64_t ctlp_ro:1; 327 uint64_t inta_map:2; 328 uint64_t intb_map:2; 329 uint64_t intc_map:2; 330 uint64_t intd_map:2; 331 uint64_t waitl_com:1; 332 uint64_t dis_port:1; 333 uint64_t inta:1; 334 uint64_t intb:1; 335 uint64_t intc:1; 336 uint64_t intd:1; 337 uint64_t reserved_22_63:42; 338#endif 339 } s; 340 struct cvmx_sli_ctl_portx_s cn61xx; 341 struct cvmx_sli_ctl_portx_s cn63xx; 342 struct cvmx_sli_ctl_portx_s cn63xxp1; 343 struct cvmx_sli_ctl_portx_s cn66xx; 344 struct cvmx_sli_ctl_portx_s cn68xx; 345 struct cvmx_sli_ctl_portx_s cn68xxp1; 346 struct cvmx_sli_ctl_portx_s cnf71xx; 347}; 348 349union cvmx_sli_ctl_status { 350 uint64_t u64; 351 struct cvmx_sli_ctl_status_s { 352#ifdef __BIG_ENDIAN_BITFIELD 353 uint64_t reserved_20_63:44; 354 uint64_t p1_ntags:6; 355 uint64_t p0_ntags:6; 356 uint64_t chip_rev:8; 357#else 358 uint64_t chip_rev:8; 359 uint64_t p0_ntags:6; 360 uint64_t p1_ntags:6; 361 uint64_t reserved_20_63:44; 362#endif 363 } s; 364 struct cvmx_sli_ctl_status_cn61xx { 365#ifdef __BIG_ENDIAN_BITFIELD 366 uint64_t reserved_14_63:50; 367 uint64_t p0_ntags:6; 368 uint64_t chip_rev:8; 369#else 370 uint64_t chip_rev:8; 371 uint64_t p0_ntags:6; 372 uint64_t reserved_14_63:50; 373#endif 374 } cn61xx; 375 struct cvmx_sli_ctl_status_s cn63xx; 376 struct cvmx_sli_ctl_status_s cn63xxp1; 377 struct cvmx_sli_ctl_status_cn61xx cn66xx; 378 struct cvmx_sli_ctl_status_s cn68xx; 379 struct cvmx_sli_ctl_status_s cn68xxp1; 380 struct cvmx_sli_ctl_status_cn61xx cnf71xx; 381}; 382 383union cvmx_sli_data_out_cnt { 384 uint64_t u64; 385 struct cvmx_sli_data_out_cnt_s { 386#ifdef __BIG_ENDIAN_BITFIELD 387 uint64_t reserved_44_63:20; 388 uint64_t p1_ucnt:16; 389 uint64_t p1_fcnt:6; 390 uint64_t p0_ucnt:16; 391 uint64_t p0_fcnt:6; 392#else 393 uint64_t p0_fcnt:6; 394 uint64_t p0_ucnt:16; 395 uint64_t p1_fcnt:6; 396 uint64_t p1_ucnt:16; 397 uint64_t reserved_44_63:20; 398#endif 399 } s; 400 struct cvmx_sli_data_out_cnt_s cn61xx; 401 struct cvmx_sli_data_out_cnt_s cn63xx; 402 struct cvmx_sli_data_out_cnt_s cn63xxp1; 403 struct cvmx_sli_data_out_cnt_s cn66xx; 404 struct cvmx_sli_data_out_cnt_s cn68xx; 405 struct cvmx_sli_data_out_cnt_s cn68xxp1; 406 struct cvmx_sli_data_out_cnt_s cnf71xx; 407}; 408 409union cvmx_sli_dbg_data { 410 uint64_t u64; 411 struct cvmx_sli_dbg_data_s { 412#ifdef __BIG_ENDIAN_BITFIELD 413 uint64_t reserved_18_63:46; 414 uint64_t dsel_ext:1; 415 uint64_t data:17; 416#else 417 uint64_t data:17; 418 uint64_t dsel_ext:1; 419 uint64_t reserved_18_63:46; 420#endif 421 } s; 422 struct cvmx_sli_dbg_data_s cn61xx; 423 struct cvmx_sli_dbg_data_s cn63xx; 424 struct cvmx_sli_dbg_data_s cn63xxp1; 425 struct cvmx_sli_dbg_data_s cn66xx; 426 struct cvmx_sli_dbg_data_s cn68xx; 427 struct cvmx_sli_dbg_data_s cn68xxp1; 428 struct cvmx_sli_dbg_data_s cnf71xx; 429}; 430 431union cvmx_sli_dbg_select { 432 uint64_t u64; 433 struct cvmx_sli_dbg_select_s { 434#ifdef __BIG_ENDIAN_BITFIELD 435 uint64_t reserved_33_63:31; 436 uint64_t adbg_sel:1; 437 uint64_t dbg_sel:32; 438#else 439 uint64_t dbg_sel:32; 440 uint64_t adbg_sel:1; 441 uint64_t reserved_33_63:31; 442#endif 443 } s; 444 struct cvmx_sli_dbg_select_s cn61xx; 445 struct cvmx_sli_dbg_select_s cn63xx; 446 struct cvmx_sli_dbg_select_s cn63xxp1; 447 struct cvmx_sli_dbg_select_s cn66xx; 448 struct cvmx_sli_dbg_select_s cn68xx; 449 struct cvmx_sli_dbg_select_s cn68xxp1; 450 struct cvmx_sli_dbg_select_s cnf71xx; 451}; 452 453union cvmx_sli_dmax_cnt { 454 uint64_t u64; 455 struct cvmx_sli_dmax_cnt_s { 456#ifdef __BIG_ENDIAN_BITFIELD 457 uint64_t reserved_32_63:32; 458 uint64_t cnt:32; 459#else 460 uint64_t cnt:32; 461 uint64_t reserved_32_63:32; 462#endif 463 } s; 464 struct cvmx_sli_dmax_cnt_s cn61xx; 465 struct cvmx_sli_dmax_cnt_s cn63xx; 466 struct cvmx_sli_dmax_cnt_s cn63xxp1; 467 struct cvmx_sli_dmax_cnt_s cn66xx; 468 struct cvmx_sli_dmax_cnt_s cn68xx; 469 struct cvmx_sli_dmax_cnt_s cn68xxp1; 470 struct cvmx_sli_dmax_cnt_s cnf71xx; 471}; 472 473union cvmx_sli_dmax_int_level { 474 uint64_t u64; 475 struct cvmx_sli_dmax_int_level_s { 476#ifdef __BIG_ENDIAN_BITFIELD 477 uint64_t time:32; 478 uint64_t cnt:32; 479#else 480 uint64_t cnt:32; 481 uint64_t time:32; 482#endif 483 } s; 484 struct cvmx_sli_dmax_int_level_s cn61xx; 485 struct cvmx_sli_dmax_int_level_s cn63xx; 486 struct cvmx_sli_dmax_int_level_s cn63xxp1; 487 struct cvmx_sli_dmax_int_level_s cn66xx; 488 struct cvmx_sli_dmax_int_level_s cn68xx; 489 struct cvmx_sli_dmax_int_level_s cn68xxp1; 490 struct cvmx_sli_dmax_int_level_s cnf71xx; 491}; 492 493union cvmx_sli_dmax_tim { 494 uint64_t u64; 495 struct cvmx_sli_dmax_tim_s { 496#ifdef __BIG_ENDIAN_BITFIELD 497 uint64_t reserved_32_63:32; 498 uint64_t tim:32; 499#else 500 uint64_t tim:32; 501 uint64_t reserved_32_63:32; 502#endif 503 } s; 504 struct cvmx_sli_dmax_tim_s cn61xx; 505 struct cvmx_sli_dmax_tim_s cn63xx; 506 struct cvmx_sli_dmax_tim_s cn63xxp1; 507 struct cvmx_sli_dmax_tim_s cn66xx; 508 struct cvmx_sli_dmax_tim_s cn68xx; 509 struct cvmx_sli_dmax_tim_s cn68xxp1; 510 struct cvmx_sli_dmax_tim_s cnf71xx; 511}; 512 513union cvmx_sli_int_enb_ciu { 514 uint64_t u64; 515 struct cvmx_sli_int_enb_ciu_s { 516#ifdef __BIG_ENDIAN_BITFIELD 517 uint64_t reserved_62_63:2; 518 uint64_t pipe_err:1; 519 uint64_t ill_pad:1; 520 uint64_t sprt3_err:1; 521 uint64_t sprt2_err:1; 522 uint64_t sprt1_err:1; 523 uint64_t sprt0_err:1; 524 uint64_t pins_err:1; 525 uint64_t pop_err:1; 526 uint64_t pdi_err:1; 527 uint64_t pgl_err:1; 528 uint64_t pin_bp:1; 529 uint64_t pout_err:1; 530 uint64_t psldbof:1; 531 uint64_t pidbof:1; 532 uint64_t reserved_38_47:10; 533 uint64_t dtime:2; 534 uint64_t dcnt:2; 535 uint64_t dmafi:2; 536 uint64_t reserved_28_31:4; 537 uint64_t m3_un_wi:1; 538 uint64_t m3_un_b0:1; 539 uint64_t m3_up_wi:1; 540 uint64_t m3_up_b0:1; 541 uint64_t m2_un_wi:1; 542 uint64_t m2_un_b0:1; 543 uint64_t m2_up_wi:1; 544 uint64_t m2_up_b0:1; 545 uint64_t reserved_18_19:2; 546 uint64_t mio_int1:1; 547 uint64_t mio_int0:1; 548 uint64_t m1_un_wi:1; 549 uint64_t m1_un_b0:1; 550 uint64_t m1_up_wi:1; 551 uint64_t m1_up_b0:1; 552 uint64_t m0_un_wi:1; 553 uint64_t m0_un_b0:1; 554 uint64_t m0_up_wi:1; 555 uint64_t m0_up_b0:1; 556 uint64_t reserved_6_7:2; 557 uint64_t ptime:1; 558 uint64_t pcnt:1; 559 uint64_t iob2big:1; 560 uint64_t bar0_to:1; 561 uint64_t reserved_1_1:1; 562 uint64_t rml_to:1; 563#else 564 uint64_t rml_to:1; 565 uint64_t reserved_1_1:1; 566 uint64_t bar0_to:1; 567 uint64_t iob2big:1; 568 uint64_t pcnt:1; 569 uint64_t ptime:1; 570 uint64_t reserved_6_7:2; 571 uint64_t m0_up_b0:1; 572 uint64_t m0_up_wi:1; 573 uint64_t m0_un_b0:1; 574 uint64_t m0_un_wi:1; 575 uint64_t m1_up_b0:1; 576 uint64_t m1_up_wi:1; 577 uint64_t m1_un_b0:1; 578 uint64_t m1_un_wi:1; 579 uint64_t mio_int0:1; 580 uint64_t mio_int1:1; 581 uint64_t reserved_18_19:2; 582 uint64_t m2_up_b0:1; 583 uint64_t m2_up_wi:1; 584 uint64_t m2_un_b0:1; 585 uint64_t m2_un_wi:1; 586 uint64_t m3_up_b0:1; 587 uint64_t m3_up_wi:1; 588 uint64_t m3_un_b0:1; 589 uint64_t m3_un_wi:1; 590 uint64_t reserved_28_31:4; 591 uint64_t dmafi:2; 592 uint64_t dcnt:2; 593 uint64_t dtime:2; 594 uint64_t reserved_38_47:10; 595 uint64_t pidbof:1; 596 uint64_t psldbof:1; 597 uint64_t pout_err:1; 598 uint64_t pin_bp:1; 599 uint64_t pgl_err:1; 600 uint64_t pdi_err:1; 601 uint64_t pop_err:1; 602 uint64_t pins_err:1; 603 uint64_t sprt0_err:1; 604 uint64_t sprt1_err:1; 605 uint64_t sprt2_err:1; 606 uint64_t sprt3_err:1; 607 uint64_t ill_pad:1; 608 uint64_t pipe_err:1; 609 uint64_t reserved_62_63:2; 610#endif 611 } s; 612 struct cvmx_sli_int_enb_ciu_cn61xx { 613#ifdef __BIG_ENDIAN_BITFIELD 614 uint64_t reserved_61_63:3; 615 uint64_t ill_pad:1; 616 uint64_t sprt3_err:1; 617 uint64_t sprt2_err:1; 618 uint64_t sprt1_err:1; 619 uint64_t sprt0_err:1; 620 uint64_t pins_err:1; 621 uint64_t pop_err:1; 622 uint64_t pdi_err:1; 623 uint64_t pgl_err:1; 624 uint64_t pin_bp:1; 625 uint64_t pout_err:1; 626 uint64_t psldbof:1; 627 uint64_t pidbof:1; 628 uint64_t reserved_38_47:10; 629 uint64_t dtime:2; 630 uint64_t dcnt:2; 631 uint64_t dmafi:2; 632 uint64_t reserved_28_31:4; 633 uint64_t m3_un_wi:1; 634 uint64_t m3_un_b0:1; 635 uint64_t m3_up_wi:1; 636 uint64_t m3_up_b0:1; 637 uint64_t m2_un_wi:1; 638 uint64_t m2_un_b0:1; 639 uint64_t m2_up_wi:1; 640 uint64_t m2_up_b0:1; 641 uint64_t reserved_18_19:2; 642 uint64_t mio_int1:1; 643 uint64_t mio_int0:1; 644 uint64_t m1_un_wi:1; 645 uint64_t m1_un_b0:1; 646 uint64_t m1_up_wi:1; 647 uint64_t m1_up_b0:1; 648 uint64_t m0_un_wi:1; 649 uint64_t m0_un_b0:1; 650 uint64_t m0_up_wi:1; 651 uint64_t m0_up_b0:1; 652 uint64_t reserved_6_7:2; 653 uint64_t ptime:1; 654 uint64_t pcnt:1; 655 uint64_t iob2big:1; 656 uint64_t bar0_to:1; 657 uint64_t reserved_1_1:1; 658 uint64_t rml_to:1; 659#else 660 uint64_t rml_to:1; 661 uint64_t reserved_1_1:1; 662 uint64_t bar0_to:1; 663 uint64_t iob2big:1; 664 uint64_t pcnt:1; 665 uint64_t ptime:1; 666 uint64_t reserved_6_7:2; 667 uint64_t m0_up_b0:1; 668 uint64_t m0_up_wi:1; 669 uint64_t m0_un_b0:1; 670 uint64_t m0_un_wi:1; 671 uint64_t m1_up_b0:1; 672 uint64_t m1_up_wi:1; 673 uint64_t m1_un_b0:1; 674 uint64_t m1_un_wi:1; 675 uint64_t mio_int0:1; 676 uint64_t mio_int1:1; 677 uint64_t reserved_18_19:2; 678 uint64_t m2_up_b0:1; 679 uint64_t m2_up_wi:1; 680 uint64_t m2_un_b0:1; 681 uint64_t m2_un_wi:1; 682 uint64_t m3_up_b0:1; 683 uint64_t m3_up_wi:1; 684 uint64_t m3_un_b0:1; 685 uint64_t m3_un_wi:1; 686 uint64_t reserved_28_31:4; 687 uint64_t dmafi:2; 688 uint64_t dcnt:2; 689 uint64_t dtime:2; 690 uint64_t reserved_38_47:10; 691 uint64_t pidbof:1; 692 uint64_t psldbof:1; 693 uint64_t pout_err:1; 694 uint64_t pin_bp:1; 695 uint64_t pgl_err:1; 696 uint64_t pdi_err:1; 697 uint64_t pop_err:1; 698 uint64_t pins_err:1; 699 uint64_t sprt0_err:1; 700 uint64_t sprt1_err:1; 701 uint64_t sprt2_err:1; 702 uint64_t sprt3_err:1; 703 uint64_t ill_pad:1; 704 uint64_t reserved_61_63:3; 705#endif 706 } cn61xx; 707 struct cvmx_sli_int_enb_ciu_cn63xx { 708#ifdef __BIG_ENDIAN_BITFIELD 709 uint64_t reserved_61_63:3; 710 uint64_t ill_pad:1; 711 uint64_t reserved_58_59:2; 712 uint64_t sprt1_err:1; 713 uint64_t sprt0_err:1; 714 uint64_t pins_err:1; 715 uint64_t pop_err:1; 716 uint64_t pdi_err:1; 717 uint64_t pgl_err:1; 718 uint64_t pin_bp:1; 719 uint64_t pout_err:1; 720 uint64_t psldbof:1; 721 uint64_t pidbof:1; 722 uint64_t reserved_38_47:10; 723 uint64_t dtime:2; 724 uint64_t dcnt:2; 725 uint64_t dmafi:2; 726 uint64_t reserved_18_31:14; 727 uint64_t mio_int1:1; 728 uint64_t mio_int0:1; 729 uint64_t m1_un_wi:1; 730 uint64_t m1_un_b0:1; 731 uint64_t m1_up_wi:1; 732 uint64_t m1_up_b0:1; 733 uint64_t m0_un_wi:1; 734 uint64_t m0_un_b0:1; 735 uint64_t m0_up_wi:1; 736 uint64_t m0_up_b0:1; 737 uint64_t reserved_6_7:2; 738 uint64_t ptime:1; 739 uint64_t pcnt:1; 740 uint64_t iob2big:1; 741 uint64_t bar0_to:1; 742 uint64_t reserved_1_1:1; 743 uint64_t rml_to:1; 744#else 745 uint64_t rml_to:1; 746 uint64_t reserved_1_1:1; 747 uint64_t bar0_to:1; 748 uint64_t iob2big:1; 749 uint64_t pcnt:1; 750 uint64_t ptime:1; 751 uint64_t reserved_6_7:2; 752 uint64_t m0_up_b0:1; 753 uint64_t m0_up_wi:1; 754 uint64_t m0_un_b0:1; 755 uint64_t m0_un_wi:1; 756 uint64_t m1_up_b0:1; 757 uint64_t m1_up_wi:1; 758 uint64_t m1_un_b0:1; 759 uint64_t m1_un_wi:1; 760 uint64_t mio_int0:1; 761 uint64_t mio_int1:1; 762 uint64_t reserved_18_31:14; 763 uint64_t dmafi:2; 764 uint64_t dcnt:2; 765 uint64_t dtime:2; 766 uint64_t reserved_38_47:10; 767 uint64_t pidbof:1; 768 uint64_t psldbof:1; 769 uint64_t pout_err:1; 770 uint64_t pin_bp:1; 771 uint64_t pgl_err:1; 772 uint64_t pdi_err:1; 773 uint64_t pop_err:1; 774 uint64_t pins_err:1; 775 uint64_t sprt0_err:1; 776 uint64_t sprt1_err:1; 777 uint64_t reserved_58_59:2; 778 uint64_t ill_pad:1; 779 uint64_t reserved_61_63:3; 780#endif 781 } cn63xx; 782 struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1; 783 struct cvmx_sli_int_enb_ciu_cn61xx cn66xx; 784 struct cvmx_sli_int_enb_ciu_cn68xx { 785#ifdef __BIG_ENDIAN_BITFIELD 786 uint64_t reserved_62_63:2; 787 uint64_t pipe_err:1; 788 uint64_t ill_pad:1; 789 uint64_t reserved_58_59:2; 790 uint64_t sprt1_err:1; 791 uint64_t sprt0_err:1; 792 uint64_t pins_err:1; 793 uint64_t pop_err:1; 794 uint64_t pdi_err:1; 795 uint64_t pgl_err:1; 796 uint64_t reserved_51_51:1; 797 uint64_t pout_err:1; 798 uint64_t psldbof:1; 799 uint64_t pidbof:1; 800 uint64_t reserved_38_47:10; 801 uint64_t dtime:2; 802 uint64_t dcnt:2; 803 uint64_t dmafi:2; 804 uint64_t reserved_18_31:14; 805 uint64_t mio_int1:1; 806 uint64_t mio_int0:1; 807 uint64_t m1_un_wi:1; 808 uint64_t m1_un_b0:1; 809 uint64_t m1_up_wi:1; 810 uint64_t m1_up_b0:1; 811 uint64_t m0_un_wi:1; 812 uint64_t m0_un_b0:1; 813 uint64_t m0_up_wi:1; 814 uint64_t m0_up_b0:1; 815 uint64_t reserved_6_7:2; 816 uint64_t ptime:1; 817 uint64_t pcnt:1; 818 uint64_t iob2big:1; 819 uint64_t bar0_to:1; 820 uint64_t reserved_1_1:1; 821 uint64_t rml_to:1; 822#else 823 uint64_t rml_to:1; 824 uint64_t reserved_1_1:1; 825 uint64_t bar0_to:1; 826 uint64_t iob2big:1; 827 uint64_t pcnt:1; 828 uint64_t ptime:1; 829 uint64_t reserved_6_7:2; 830 uint64_t m0_up_b0:1; 831 uint64_t m0_up_wi:1; 832 uint64_t m0_un_b0:1; 833 uint64_t m0_un_wi:1; 834 uint64_t m1_up_b0:1; 835 uint64_t m1_up_wi:1; 836 uint64_t m1_un_b0:1; 837 uint64_t m1_un_wi:1; 838 uint64_t mio_int0:1; 839 uint64_t mio_int1:1; 840 uint64_t reserved_18_31:14; 841 uint64_t dmafi:2; 842 uint64_t dcnt:2; 843 uint64_t dtime:2; 844 uint64_t reserved_38_47:10; 845 uint64_t pidbof:1; 846 uint64_t psldbof:1; 847 uint64_t pout_err:1; 848 uint64_t reserved_51_51:1; 849 uint64_t pgl_err:1; 850 uint64_t pdi_err:1; 851 uint64_t pop_err:1; 852 uint64_t pins_err:1; 853 uint64_t sprt0_err:1; 854 uint64_t sprt1_err:1; 855 uint64_t reserved_58_59:2; 856 uint64_t ill_pad:1; 857 uint64_t pipe_err:1; 858 uint64_t reserved_62_63:2; 859#endif 860 } cn68xx; 861 struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1; 862 struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx; 863}; 864 865union cvmx_sli_int_enb_portx { 866 uint64_t u64; 867 struct cvmx_sli_int_enb_portx_s { 868#ifdef __BIG_ENDIAN_BITFIELD 869 uint64_t reserved_62_63:2; 870 uint64_t pipe_err:1; 871 uint64_t ill_pad:1; 872 uint64_t sprt3_err:1; 873 uint64_t sprt2_err:1; 874 uint64_t sprt1_err:1; 875 uint64_t sprt0_err:1; 876 uint64_t pins_err:1; 877 uint64_t pop_err:1; 878 uint64_t pdi_err:1; 879 uint64_t pgl_err:1; 880 uint64_t pin_bp:1; 881 uint64_t pout_err:1; 882 uint64_t psldbof:1; 883 uint64_t pidbof:1; 884 uint64_t reserved_38_47:10; 885 uint64_t dtime:2; 886 uint64_t dcnt:2; 887 uint64_t dmafi:2; 888 uint64_t reserved_28_31:4; 889 uint64_t m3_un_wi:1; 890 uint64_t m3_un_b0:1; 891 uint64_t m3_up_wi:1; 892 uint64_t m3_up_b0:1; 893 uint64_t m2_un_wi:1; 894 uint64_t m2_un_b0:1; 895 uint64_t m2_up_wi:1; 896 uint64_t m2_up_b0:1; 897 uint64_t mac1_int:1; 898 uint64_t mac0_int:1; 899 uint64_t mio_int1:1; 900 uint64_t mio_int0:1; 901 uint64_t m1_un_wi:1; 902 uint64_t m1_un_b0:1; 903 uint64_t m1_up_wi:1; 904 uint64_t m1_up_b0:1; 905 uint64_t m0_un_wi:1; 906 uint64_t m0_un_b0:1; 907 uint64_t m0_up_wi:1; 908 uint64_t m0_up_b0:1; 909 uint64_t reserved_6_7:2; 910 uint64_t ptime:1; 911 uint64_t pcnt:1; 912 uint64_t iob2big:1; 913 uint64_t bar0_to:1; 914 uint64_t reserved_1_1:1; 915 uint64_t rml_to:1; 916#else 917 uint64_t rml_to:1; 918 uint64_t reserved_1_1:1; 919 uint64_t bar0_to:1; 920 uint64_t iob2big:1; 921 uint64_t pcnt:1; 922 uint64_t ptime:1; 923 uint64_t reserved_6_7:2; 924 uint64_t m0_up_b0:1; 925 uint64_t m0_up_wi:1; 926 uint64_t m0_un_b0:1; 927 uint64_t m0_un_wi:1; 928 uint64_t m1_up_b0:1; 929 uint64_t m1_up_wi:1; 930 uint64_t m1_un_b0:1; 931 uint64_t m1_un_wi:1; 932 uint64_t mio_int0:1; 933 uint64_t mio_int1:1; 934 uint64_t mac0_int:1; 935 uint64_t mac1_int:1; 936 uint64_t m2_up_b0:1; 937 uint64_t m2_up_wi:1; 938 uint64_t m2_un_b0:1; 939 uint64_t m2_un_wi:1; 940 uint64_t m3_up_b0:1; 941 uint64_t m3_up_wi:1; 942 uint64_t m3_un_b0:1; 943 uint64_t m3_un_wi:1; 944 uint64_t reserved_28_31:4; 945 uint64_t dmafi:2; 946 uint64_t dcnt:2; 947 uint64_t dtime:2; 948 uint64_t reserved_38_47:10; 949 uint64_t pidbof:1; 950 uint64_t psldbof:1; 951 uint64_t pout_err:1; 952 uint64_t pin_bp:1; 953 uint64_t pgl_err:1; 954 uint64_t pdi_err:1; 955 uint64_t pop_err:1; 956 uint64_t pins_err:1; 957 uint64_t sprt0_err:1; 958 uint64_t sprt1_err:1; 959 uint64_t sprt2_err:1; 960 uint64_t sprt3_err:1; 961 uint64_t ill_pad:1; 962 uint64_t pipe_err:1; 963 uint64_t reserved_62_63:2; 964#endif 965 } s; 966 struct cvmx_sli_int_enb_portx_cn61xx { 967#ifdef __BIG_ENDIAN_BITFIELD 968 uint64_t reserved_61_63:3; 969 uint64_t ill_pad:1; 970 uint64_t sprt3_err:1; 971 uint64_t sprt2_err:1; 972 uint64_t sprt1_err:1; 973 uint64_t sprt0_err:1; 974 uint64_t pins_err:1; 975 uint64_t pop_err:1; 976 uint64_t pdi_err:1; 977 uint64_t pgl_err:1; 978 uint64_t pin_bp:1; 979 uint64_t pout_err:1; 980 uint64_t psldbof:1; 981 uint64_t pidbof:1; 982 uint64_t reserved_38_47:10; 983 uint64_t dtime:2; 984 uint64_t dcnt:2; 985 uint64_t dmafi:2; 986 uint64_t reserved_28_31:4; 987 uint64_t m3_un_wi:1; 988 uint64_t m3_un_b0:1; 989 uint64_t m3_up_wi:1; 990 uint64_t m3_up_b0:1; 991 uint64_t m2_un_wi:1; 992 uint64_t m2_un_b0:1; 993 uint64_t m2_up_wi:1; 994 uint64_t m2_up_b0:1; 995 uint64_t mac1_int:1; 996 uint64_t mac0_int:1; 997 uint64_t mio_int1:1; 998 uint64_t mio_int0:1; 999 uint64_t m1_un_wi:1; 1000 uint64_t m1_un_b0:1; 1001 uint64_t m1_up_wi:1; 1002 uint64_t m1_up_b0:1; 1003 uint64_t m0_un_wi:1; 1004 uint64_t m0_un_b0:1; 1005 uint64_t m0_up_wi:1; 1006 uint64_t m0_up_b0:1; 1007 uint64_t reserved_6_7:2; 1008 uint64_t ptime:1; 1009 uint64_t pcnt:1; 1010 uint64_t iob2big:1; 1011 uint64_t bar0_to:1; 1012 uint64_t reserved_1_1:1; 1013 uint64_t rml_to:1; 1014#else 1015 uint64_t rml_to:1; 1016 uint64_t reserved_1_1:1; 1017 uint64_t bar0_to:1; 1018 uint64_t iob2big:1; 1019 uint64_t pcnt:1; 1020 uint64_t ptime:1; 1021 uint64_t reserved_6_7:2; 1022 uint64_t m0_up_b0:1; 1023 uint64_t m0_up_wi:1; 1024 uint64_t m0_un_b0:1; 1025 uint64_t m0_un_wi:1; 1026 uint64_t m1_up_b0:1; 1027 uint64_t m1_up_wi:1; 1028 uint64_t m1_un_b0:1; 1029 uint64_t m1_un_wi:1; 1030 uint64_t mio_int0:1; 1031 uint64_t mio_int1:1; 1032 uint64_t mac0_int:1; 1033 uint64_t mac1_int:1; 1034 uint64_t m2_up_b0:1; 1035 uint64_t m2_up_wi:1; 1036 uint64_t m2_un_b0:1; 1037 uint64_t m2_un_wi:1; 1038 uint64_t m3_up_b0:1; 1039 uint64_t m3_up_wi:1; 1040 uint64_t m3_un_b0:1; 1041 uint64_t m3_un_wi:1; 1042 uint64_t reserved_28_31:4; 1043 uint64_t dmafi:2; 1044 uint64_t dcnt:2; 1045 uint64_t dtime:2; 1046 uint64_t reserved_38_47:10; 1047 uint64_t pidbof:1; 1048 uint64_t psldbof:1; 1049 uint64_t pout_err:1; 1050 uint64_t pin_bp:1; 1051 uint64_t pgl_err:1; 1052 uint64_t pdi_err:1; 1053 uint64_t pop_err:1; 1054 uint64_t pins_err:1; 1055 uint64_t sprt0_err:1; 1056 uint64_t sprt1_err:1; 1057 uint64_t sprt2_err:1; 1058 uint64_t sprt3_err:1; 1059 uint64_t ill_pad:1; 1060 uint64_t reserved_61_63:3; 1061#endif 1062 } cn61xx; 1063 struct cvmx_sli_int_enb_portx_cn63xx { 1064#ifdef __BIG_ENDIAN_BITFIELD 1065 uint64_t reserved_61_63:3; 1066 uint64_t ill_pad:1; 1067 uint64_t reserved_58_59:2; 1068 uint64_t sprt1_err:1; 1069 uint64_t sprt0_err:1; 1070 uint64_t pins_err:1; 1071 uint64_t pop_err:1; 1072 uint64_t pdi_err:1; 1073 uint64_t pgl_err:1; 1074 uint64_t pin_bp:1; 1075 uint64_t pout_err:1; 1076 uint64_t psldbof:1; 1077 uint64_t pidbof:1; 1078 uint64_t reserved_38_47:10; 1079 uint64_t dtime:2; 1080 uint64_t dcnt:2; 1081 uint64_t dmafi:2; 1082 uint64_t reserved_20_31:12; 1083 uint64_t mac1_int:1; 1084 uint64_t mac0_int:1; 1085 uint64_t mio_int1:1; 1086 uint64_t mio_int0:1; 1087 uint64_t m1_un_wi:1; 1088 uint64_t m1_un_b0:1; 1089 uint64_t m1_up_wi:1; 1090 uint64_t m1_up_b0:1; 1091 uint64_t m0_un_wi:1; 1092 uint64_t m0_un_b0:1; 1093 uint64_t m0_up_wi:1; 1094 uint64_t m0_up_b0:1; 1095 uint64_t reserved_6_7:2; 1096 uint64_t ptime:1; 1097 uint64_t pcnt:1; 1098 uint64_t iob2big:1; 1099 uint64_t bar0_to:1; 1100 uint64_t reserved_1_1:1; 1101 uint64_t rml_to:1; 1102#else 1103 uint64_t rml_to:1; 1104 uint64_t reserved_1_1:1; 1105 uint64_t bar0_to:1; 1106 uint64_t iob2big:1; 1107 uint64_t pcnt:1; 1108 uint64_t ptime:1; 1109 uint64_t reserved_6_7:2; 1110 uint64_t m0_up_b0:1; 1111 uint64_t m0_up_wi:1; 1112 uint64_t m0_un_b0:1; 1113 uint64_t m0_un_wi:1; 1114 uint64_t m1_up_b0:1; 1115 uint64_t m1_up_wi:1; 1116 uint64_t m1_un_b0:1; 1117 uint64_t m1_un_wi:1; 1118 uint64_t mio_int0:1; 1119 uint64_t mio_int1:1; 1120 uint64_t mac0_int:1; 1121 uint64_t mac1_int:1; 1122 uint64_t reserved_20_31:12; 1123 uint64_t dmafi:2; 1124 uint64_t dcnt:2; 1125 uint64_t dtime:2; 1126 uint64_t reserved_38_47:10; 1127 uint64_t pidbof:1; 1128 uint64_t psldbof:1; 1129 uint64_t pout_err:1; 1130 uint64_t pin_bp:1; 1131 uint64_t pgl_err:1; 1132 uint64_t pdi_err:1; 1133 uint64_t pop_err:1; 1134 uint64_t pins_err:1; 1135 uint64_t sprt0_err:1; 1136 uint64_t sprt1_err:1; 1137 uint64_t reserved_58_59:2; 1138 uint64_t ill_pad:1; 1139 uint64_t reserved_61_63:3; 1140#endif 1141 } cn63xx; 1142 struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1; 1143 struct cvmx_sli_int_enb_portx_cn61xx cn66xx; 1144 struct cvmx_sli_int_enb_portx_cn68xx { 1145#ifdef __BIG_ENDIAN_BITFIELD 1146 uint64_t reserved_62_63:2; 1147 uint64_t pipe_err:1; 1148 uint64_t ill_pad:1; 1149 uint64_t reserved_58_59:2; 1150 uint64_t sprt1_err:1; 1151 uint64_t sprt0_err:1; 1152 uint64_t pins_err:1; 1153 uint64_t pop_err:1; 1154 uint64_t pdi_err:1; 1155 uint64_t pgl_err:1; 1156 uint64_t reserved_51_51:1; 1157 uint64_t pout_err:1; 1158 uint64_t psldbof:1; 1159 uint64_t pidbof:1; 1160 uint64_t reserved_38_47:10; 1161 uint64_t dtime:2; 1162 uint64_t dcnt:2; 1163 uint64_t dmafi:2; 1164 uint64_t reserved_20_31:12; 1165 uint64_t mac1_int:1; 1166 uint64_t mac0_int:1; 1167 uint64_t mio_int1:1; 1168 uint64_t mio_int0:1; 1169 uint64_t m1_un_wi:1; 1170 uint64_t m1_un_b0:1; 1171 uint64_t m1_up_wi:1; 1172 uint64_t m1_up_b0:1; 1173 uint64_t m0_un_wi:1; 1174 uint64_t m0_un_b0:1; 1175 uint64_t m0_up_wi:1; 1176 uint64_t m0_up_b0:1; 1177 uint64_t reserved_6_7:2; 1178 uint64_t ptime:1; 1179 uint64_t pcnt:1; 1180 uint64_t iob2big:1; 1181 uint64_t bar0_to:1; 1182 uint64_t reserved_1_1:1; 1183 uint64_t rml_to:1; 1184#else 1185 uint64_t rml_to:1; 1186 uint64_t reserved_1_1:1; 1187 uint64_t bar0_to:1; 1188 uint64_t iob2big:1; 1189 uint64_t pcnt:1; 1190 uint64_t ptime:1; 1191 uint64_t reserved_6_7:2; 1192 uint64_t m0_up_b0:1; 1193 uint64_t m0_up_wi:1; 1194 uint64_t m0_un_b0:1; 1195 uint64_t m0_un_wi:1; 1196 uint64_t m1_up_b0:1; 1197 uint64_t m1_up_wi:1; 1198 uint64_t m1_un_b0:1; 1199 uint64_t m1_un_wi:1; 1200 uint64_t mio_int0:1; 1201 uint64_t mio_int1:1; 1202 uint64_t mac0_int:1; 1203 uint64_t mac1_int:1; 1204 uint64_t reserved_20_31:12; 1205 uint64_t dmafi:2; 1206 uint64_t dcnt:2; 1207 uint64_t dtime:2; 1208 uint64_t reserved_38_47:10; 1209 uint64_t pidbof:1; 1210 uint64_t psldbof:1; 1211 uint64_t pout_err:1; 1212 uint64_t reserved_51_51:1; 1213 uint64_t pgl_err:1; 1214 uint64_t pdi_err:1; 1215 uint64_t pop_err:1; 1216 uint64_t pins_err:1; 1217 uint64_t sprt0_err:1; 1218 uint64_t sprt1_err:1; 1219 uint64_t reserved_58_59:2; 1220 uint64_t ill_pad:1; 1221 uint64_t pipe_err:1; 1222 uint64_t reserved_62_63:2; 1223#endif 1224 } cn68xx; 1225 struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1; 1226 struct cvmx_sli_int_enb_portx_cn61xx cnf71xx; 1227}; 1228 1229union cvmx_sli_int_sum { 1230 uint64_t u64; 1231 struct cvmx_sli_int_sum_s { 1232#ifdef __BIG_ENDIAN_BITFIELD 1233 uint64_t reserved_62_63:2; 1234 uint64_t pipe_err:1; 1235 uint64_t ill_pad:1; 1236 uint64_t sprt3_err:1; 1237 uint64_t sprt2_err:1; 1238 uint64_t sprt1_err:1; 1239 uint64_t sprt0_err:1; 1240 uint64_t pins_err:1; 1241 uint64_t pop_err:1; 1242 uint64_t pdi_err:1; 1243 uint64_t pgl_err:1; 1244 uint64_t pin_bp:1; 1245 uint64_t pout_err:1; 1246 uint64_t psldbof:1; 1247 uint64_t pidbof:1; 1248 uint64_t reserved_38_47:10; 1249 uint64_t dtime:2; 1250 uint64_t dcnt:2; 1251 uint64_t dmafi:2; 1252 uint64_t reserved_28_31:4; 1253 uint64_t m3_un_wi:1; 1254 uint64_t m3_un_b0:1; 1255 uint64_t m3_up_wi:1; 1256 uint64_t m3_up_b0:1; 1257 uint64_t m2_un_wi:1; 1258 uint64_t m2_un_b0:1; 1259 uint64_t m2_up_wi:1; 1260 uint64_t m2_up_b0:1; 1261 uint64_t mac1_int:1; 1262 uint64_t mac0_int:1; 1263 uint64_t mio_int1:1; 1264 uint64_t mio_int0:1; 1265 uint64_t m1_un_wi:1; 1266 uint64_t m1_un_b0:1; 1267 uint64_t m1_up_wi:1; 1268 uint64_t m1_up_b0:1; 1269 uint64_t m0_un_wi:1; 1270 uint64_t m0_un_b0:1; 1271 uint64_t m0_up_wi:1; 1272 uint64_t m0_up_b0:1; 1273 uint64_t reserved_6_7:2; 1274 uint64_t ptime:1; 1275 uint64_t pcnt:1; 1276 uint64_t iob2big:1; 1277 uint64_t bar0_to:1; 1278 uint64_t reserved_1_1:1; 1279 uint64_t rml_to:1; 1280#else 1281 uint64_t rml_to:1; 1282 uint64_t reserved_1_1:1; 1283 uint64_t bar0_to:1; 1284 uint64_t iob2big:1; 1285 uint64_t pcnt:1; 1286 uint64_t ptime:1; 1287 uint64_t reserved_6_7:2; 1288 uint64_t m0_up_b0:1; 1289 uint64_t m0_up_wi:1; 1290 uint64_t m0_un_b0:1; 1291 uint64_t m0_un_wi:1; 1292 uint64_t m1_up_b0:1; 1293 uint64_t m1_up_wi:1; 1294 uint64_t m1_un_b0:1; 1295 uint64_t m1_un_wi:1; 1296 uint64_t mio_int0:1; 1297 uint64_t mio_int1:1; 1298 uint64_t mac0_int:1; 1299 uint64_t mac1_int:1; 1300 uint64_t m2_up_b0:1; 1301 uint64_t m2_up_wi:1; 1302 uint64_t m2_un_b0:1; 1303 uint64_t m2_un_wi:1; 1304 uint64_t m3_up_b0:1; 1305 uint64_t m3_up_wi:1; 1306 uint64_t m3_un_b0:1; 1307 uint64_t m3_un_wi:1; 1308 uint64_t reserved_28_31:4; 1309 uint64_t dmafi:2; 1310 uint64_t dcnt:2; 1311 uint64_t dtime:2; 1312 uint64_t reserved_38_47:10; 1313 uint64_t pidbof:1; 1314 uint64_t psldbof:1; 1315 uint64_t pout_err:1; 1316 uint64_t pin_bp:1; 1317 uint64_t pgl_err:1; 1318 uint64_t pdi_err:1; 1319 uint64_t pop_err:1; 1320 uint64_t pins_err:1; 1321 uint64_t sprt0_err:1; 1322 uint64_t sprt1_err:1; 1323 uint64_t sprt2_err:1; 1324 uint64_t sprt3_err:1; 1325 uint64_t ill_pad:1; 1326 uint64_t pipe_err:1; 1327 uint64_t reserved_62_63:2; 1328#endif 1329 } s; 1330 struct cvmx_sli_int_sum_cn61xx { 1331#ifdef __BIG_ENDIAN_BITFIELD 1332 uint64_t reserved_61_63:3; 1333 uint64_t ill_pad:1; 1334 uint64_t sprt3_err:1; 1335 uint64_t sprt2_err:1; 1336 uint64_t sprt1_err:1; 1337 uint64_t sprt0_err:1; 1338 uint64_t pins_err:1; 1339 uint64_t pop_err:1; 1340 uint64_t pdi_err:1; 1341 uint64_t pgl_err:1; 1342 uint64_t pin_bp:1; 1343 uint64_t pout_err:1; 1344 uint64_t psldbof:1; 1345 uint64_t pidbof:1; 1346 uint64_t reserved_38_47:10; 1347 uint64_t dtime:2; 1348 uint64_t dcnt:2; 1349 uint64_t dmafi:2; 1350 uint64_t reserved_28_31:4; 1351 uint64_t m3_un_wi:1; 1352 uint64_t m3_un_b0:1; 1353 uint64_t m3_up_wi:1; 1354 uint64_t m3_up_b0:1; 1355 uint64_t m2_un_wi:1; 1356 uint64_t m2_un_b0:1; 1357 uint64_t m2_up_wi:1; 1358 uint64_t m2_up_b0:1; 1359 uint64_t mac1_int:1; 1360 uint64_t mac0_int:1; 1361 uint64_t mio_int1:1; 1362 uint64_t mio_int0:1; 1363 uint64_t m1_un_wi:1; 1364 uint64_t m1_un_b0:1; 1365 uint64_t m1_up_wi:1; 1366 uint64_t m1_up_b0:1; 1367 uint64_t m0_un_wi:1; 1368 uint64_t m0_un_b0:1; 1369 uint64_t m0_up_wi:1; 1370 uint64_t m0_up_b0:1; 1371 uint64_t reserved_6_7:2; 1372 uint64_t ptime:1; 1373 uint64_t pcnt:1; 1374 uint64_t iob2big:1; 1375 uint64_t bar0_to:1; 1376 uint64_t reserved_1_1:1; 1377 uint64_t rml_to:1; 1378#else 1379 uint64_t rml_to:1; 1380 uint64_t reserved_1_1:1; 1381 uint64_t bar0_to:1; 1382 uint64_t iob2big:1; 1383 uint64_t pcnt:1; 1384 uint64_t ptime:1; 1385 uint64_t reserved_6_7:2; 1386 uint64_t m0_up_b0:1; 1387 uint64_t m0_up_wi:1; 1388 uint64_t m0_un_b0:1; 1389 uint64_t m0_un_wi:1; 1390 uint64_t m1_up_b0:1; 1391 uint64_t m1_up_wi:1; 1392 uint64_t m1_un_b0:1; 1393 uint64_t m1_un_wi:1; 1394 uint64_t mio_int0:1; 1395 uint64_t mio_int1:1; 1396 uint64_t mac0_int:1; 1397 uint64_t mac1_int:1; 1398 uint64_t m2_up_b0:1; 1399 uint64_t m2_up_wi:1; 1400 uint64_t m2_un_b0:1; 1401 uint64_t m2_un_wi:1; 1402 uint64_t m3_up_b0:1; 1403 uint64_t m3_up_wi:1; 1404 uint64_t m3_un_b0:1; 1405 uint64_t m3_un_wi:1; 1406 uint64_t reserved_28_31:4; 1407 uint64_t dmafi:2; 1408 uint64_t dcnt:2; 1409 uint64_t dtime:2; 1410 uint64_t reserved_38_47:10; 1411 uint64_t pidbof:1; 1412 uint64_t psldbof:1; 1413 uint64_t pout_err:1; 1414 uint64_t pin_bp:1; 1415 uint64_t pgl_err:1; 1416 uint64_t pdi_err:1; 1417 uint64_t pop_err:1; 1418 uint64_t pins_err:1; 1419 uint64_t sprt0_err:1; 1420 uint64_t sprt1_err:1; 1421 uint64_t sprt2_err:1; 1422 uint64_t sprt3_err:1; 1423 uint64_t ill_pad:1; 1424 uint64_t reserved_61_63:3; 1425#endif 1426 } cn61xx; 1427 struct cvmx_sli_int_sum_cn63xx { 1428#ifdef __BIG_ENDIAN_BITFIELD 1429 uint64_t reserved_61_63:3; 1430 uint64_t ill_pad:1; 1431 uint64_t reserved_58_59:2; 1432 uint64_t sprt1_err:1; 1433 uint64_t sprt0_err:1; 1434 uint64_t pins_err:1; 1435 uint64_t pop_err:1; 1436 uint64_t pdi_err:1; 1437 uint64_t pgl_err:1; 1438 uint64_t pin_bp:1; 1439 uint64_t pout_err:1; 1440 uint64_t psldbof:1; 1441 uint64_t pidbof:1; 1442 uint64_t reserved_38_47:10; 1443 uint64_t dtime:2; 1444 uint64_t dcnt:2; 1445 uint64_t dmafi:2; 1446 uint64_t reserved_20_31:12; 1447 uint64_t mac1_int:1; 1448 uint64_t mac0_int:1; 1449 uint64_t mio_int1:1; 1450 uint64_t mio_int0:1; 1451 uint64_t m1_un_wi:1; 1452 uint64_t m1_un_b0:1; 1453 uint64_t m1_up_wi:1; 1454 uint64_t m1_up_b0:1; 1455 uint64_t m0_un_wi:1; 1456 uint64_t m0_un_b0:1; 1457 uint64_t m0_up_wi:1; 1458 uint64_t m0_up_b0:1; 1459 uint64_t reserved_6_7:2; 1460 uint64_t ptime:1; 1461 uint64_t pcnt:1; 1462 uint64_t iob2big:1; 1463 uint64_t bar0_to:1; 1464 uint64_t reserved_1_1:1; 1465 uint64_t rml_to:1; 1466#else 1467 uint64_t rml_to:1; 1468 uint64_t reserved_1_1:1; 1469 uint64_t bar0_to:1; 1470 uint64_t iob2big:1; 1471 uint64_t pcnt:1; 1472 uint64_t ptime:1; 1473 uint64_t reserved_6_7:2; 1474 uint64_t m0_up_b0:1; 1475 uint64_t m0_up_wi:1; 1476 uint64_t m0_un_b0:1; 1477 uint64_t m0_un_wi:1; 1478 uint64_t m1_up_b0:1; 1479 uint64_t m1_up_wi:1; 1480 uint64_t m1_un_b0:1; 1481 uint64_t m1_un_wi:1; 1482 uint64_t mio_int0:1; 1483 uint64_t mio_int1:1; 1484 uint64_t mac0_int:1; 1485 uint64_t mac1_int:1; 1486 uint64_t reserved_20_31:12; 1487 uint64_t dmafi:2; 1488 uint64_t dcnt:2; 1489 uint64_t dtime:2; 1490 uint64_t reserved_38_47:10; 1491 uint64_t pidbof:1; 1492 uint64_t psldbof:1; 1493 uint64_t pout_err:1; 1494 uint64_t pin_bp:1; 1495 uint64_t pgl_err:1; 1496 uint64_t pdi_err:1; 1497 uint64_t pop_err:1; 1498 uint64_t pins_err:1; 1499 uint64_t sprt0_err:1; 1500 uint64_t sprt1_err:1; 1501 uint64_t reserved_58_59:2; 1502 uint64_t ill_pad:1; 1503 uint64_t reserved_61_63:3; 1504#endif 1505 } cn63xx; 1506 struct cvmx_sli_int_sum_cn63xx cn63xxp1; 1507 struct cvmx_sli_int_sum_cn61xx cn66xx; 1508 struct cvmx_sli_int_sum_cn68xx { 1509#ifdef __BIG_ENDIAN_BITFIELD 1510 uint64_t reserved_62_63:2; 1511 uint64_t pipe_err:1; 1512 uint64_t ill_pad:1; 1513 uint64_t reserved_58_59:2; 1514 uint64_t sprt1_err:1; 1515 uint64_t sprt0_err:1; 1516 uint64_t pins_err:1; 1517 uint64_t pop_err:1; 1518 uint64_t pdi_err:1; 1519 uint64_t pgl_err:1; 1520 uint64_t reserved_51_51:1; 1521 uint64_t pout_err:1; 1522 uint64_t psldbof:1; 1523 uint64_t pidbof:1; 1524 uint64_t reserved_38_47:10; 1525 uint64_t dtime:2; 1526 uint64_t dcnt:2; 1527 uint64_t dmafi:2; 1528 uint64_t reserved_20_31:12; 1529 uint64_t mac1_int:1; 1530 uint64_t mac0_int:1; 1531 uint64_t mio_int1:1; 1532 uint64_t mio_int0:1; 1533 uint64_t m1_un_wi:1; 1534 uint64_t m1_un_b0:1; 1535 uint64_t m1_up_wi:1; 1536 uint64_t m1_up_b0:1; 1537 uint64_t m0_un_wi:1; 1538 uint64_t m0_un_b0:1; 1539 uint64_t m0_up_wi:1; 1540 uint64_t m0_up_b0:1; 1541 uint64_t reserved_6_7:2; 1542 uint64_t ptime:1; 1543 uint64_t pcnt:1; 1544 uint64_t iob2big:1; 1545 uint64_t bar0_to:1; 1546 uint64_t reserved_1_1:1; 1547 uint64_t rml_to:1; 1548#else 1549 uint64_t rml_to:1; 1550 uint64_t reserved_1_1:1; 1551 uint64_t bar0_to:1; 1552 uint64_t iob2big:1; 1553 uint64_t pcnt:1; 1554 uint64_t ptime:1; 1555 uint64_t reserved_6_7:2; 1556 uint64_t m0_up_b0:1; 1557 uint64_t m0_up_wi:1; 1558 uint64_t m0_un_b0:1; 1559 uint64_t m0_un_wi:1; 1560 uint64_t m1_up_b0:1; 1561 uint64_t m1_up_wi:1; 1562 uint64_t m1_un_b0:1; 1563 uint64_t m1_un_wi:1; 1564 uint64_t mio_int0:1; 1565 uint64_t mio_int1:1; 1566 uint64_t mac0_int:1; 1567 uint64_t mac1_int:1; 1568 uint64_t reserved_20_31:12; 1569 uint64_t dmafi:2; 1570 uint64_t dcnt:2; 1571 uint64_t dtime:2; 1572 uint64_t reserved_38_47:10; 1573 uint64_t pidbof:1; 1574 uint64_t psldbof:1; 1575 uint64_t pout_err:1; 1576 uint64_t reserved_51_51:1; 1577 uint64_t pgl_err:1; 1578 uint64_t pdi_err:1; 1579 uint64_t pop_err:1; 1580 uint64_t pins_err:1; 1581 uint64_t sprt0_err:1; 1582 uint64_t sprt1_err:1; 1583 uint64_t reserved_58_59:2; 1584 uint64_t ill_pad:1; 1585 uint64_t pipe_err:1; 1586 uint64_t reserved_62_63:2; 1587#endif 1588 } cn68xx; 1589 struct cvmx_sli_int_sum_cn68xx cn68xxp1; 1590 struct cvmx_sli_int_sum_cn61xx cnf71xx; 1591}; 1592 1593union cvmx_sli_last_win_rdata0 { 1594 uint64_t u64; 1595 struct cvmx_sli_last_win_rdata0_s { 1596#ifdef __BIG_ENDIAN_BITFIELD 1597 uint64_t data:64; 1598#else 1599 uint64_t data:64; 1600#endif 1601 } s; 1602 struct cvmx_sli_last_win_rdata0_s cn61xx; 1603 struct cvmx_sli_last_win_rdata0_s cn63xx; 1604 struct cvmx_sli_last_win_rdata0_s cn63xxp1; 1605 struct cvmx_sli_last_win_rdata0_s cn66xx; 1606 struct cvmx_sli_last_win_rdata0_s cn68xx; 1607 struct cvmx_sli_last_win_rdata0_s cn68xxp1; 1608 struct cvmx_sli_last_win_rdata0_s cnf71xx; 1609}; 1610 1611union cvmx_sli_last_win_rdata1 { 1612 uint64_t u64; 1613 struct cvmx_sli_last_win_rdata1_s { 1614#ifdef __BIG_ENDIAN_BITFIELD 1615 uint64_t data:64; 1616#else 1617 uint64_t data:64; 1618#endif 1619 } s; 1620 struct cvmx_sli_last_win_rdata1_s cn61xx; 1621 struct cvmx_sli_last_win_rdata1_s cn63xx; 1622 struct cvmx_sli_last_win_rdata1_s cn63xxp1; 1623 struct cvmx_sli_last_win_rdata1_s cn66xx; 1624 struct cvmx_sli_last_win_rdata1_s cn68xx; 1625 struct cvmx_sli_last_win_rdata1_s cn68xxp1; 1626 struct cvmx_sli_last_win_rdata1_s cnf71xx; 1627}; 1628 1629union cvmx_sli_last_win_rdata2 { 1630 uint64_t u64; 1631 struct cvmx_sli_last_win_rdata2_s { 1632#ifdef __BIG_ENDIAN_BITFIELD 1633 uint64_t data:64; 1634#else 1635 uint64_t data:64; 1636#endif 1637 } s; 1638 struct cvmx_sli_last_win_rdata2_s cn61xx; 1639 struct cvmx_sli_last_win_rdata2_s cn66xx; 1640 struct cvmx_sli_last_win_rdata2_s cnf71xx; 1641}; 1642 1643union cvmx_sli_last_win_rdata3 { 1644 uint64_t u64; 1645 struct cvmx_sli_last_win_rdata3_s { 1646#ifdef __BIG_ENDIAN_BITFIELD 1647 uint64_t data:64; 1648#else 1649 uint64_t data:64; 1650#endif 1651 } s; 1652 struct cvmx_sli_last_win_rdata3_s cn61xx; 1653 struct cvmx_sli_last_win_rdata3_s cn66xx; 1654 struct cvmx_sli_last_win_rdata3_s cnf71xx; 1655}; 1656 1657union cvmx_sli_mac_credit_cnt { 1658 uint64_t u64; 1659 struct cvmx_sli_mac_credit_cnt_s { 1660#ifdef __BIG_ENDIAN_BITFIELD 1661 uint64_t reserved_54_63:10; 1662 uint64_t p1_c_d:1; 1663 uint64_t p1_n_d:1; 1664 uint64_t p1_p_d:1; 1665 uint64_t p0_c_d:1; 1666 uint64_t p0_n_d:1; 1667 uint64_t p0_p_d:1; 1668 uint64_t p1_ccnt:8; 1669 uint64_t p1_ncnt:8; 1670 uint64_t p1_pcnt:8; 1671 uint64_t p0_ccnt:8; 1672 uint64_t p0_ncnt:8; 1673 uint64_t p0_pcnt:8; 1674#else 1675 uint64_t p0_pcnt:8; 1676 uint64_t p0_ncnt:8; 1677 uint64_t p0_ccnt:8; 1678 uint64_t p1_pcnt:8; 1679 uint64_t p1_ncnt:8; 1680 uint64_t p1_ccnt:8; 1681 uint64_t p0_p_d:1; 1682 uint64_t p0_n_d:1; 1683 uint64_t p0_c_d:1; 1684 uint64_t p1_p_d:1; 1685 uint64_t p1_n_d:1; 1686 uint64_t p1_c_d:1; 1687 uint64_t reserved_54_63:10; 1688#endif 1689 } s; 1690 struct cvmx_sli_mac_credit_cnt_s cn61xx; 1691 struct cvmx_sli_mac_credit_cnt_s cn63xx; 1692 struct cvmx_sli_mac_credit_cnt_cn63xxp1 { 1693#ifdef __BIG_ENDIAN_BITFIELD 1694 uint64_t reserved_48_63:16; 1695 uint64_t p1_ccnt:8; 1696 uint64_t p1_ncnt:8; 1697 uint64_t p1_pcnt:8; 1698 uint64_t p0_ccnt:8; 1699 uint64_t p0_ncnt:8; 1700 uint64_t p0_pcnt:8; 1701#else 1702 uint64_t p0_pcnt:8; 1703 uint64_t p0_ncnt:8; 1704 uint64_t p0_ccnt:8; 1705 uint64_t p1_pcnt:8; 1706 uint64_t p1_ncnt:8; 1707 uint64_t p1_ccnt:8; 1708 uint64_t reserved_48_63:16; 1709#endif 1710 } cn63xxp1; 1711 struct cvmx_sli_mac_credit_cnt_s cn66xx; 1712 struct cvmx_sli_mac_credit_cnt_s cn68xx; 1713 struct cvmx_sli_mac_credit_cnt_s cn68xxp1; 1714 struct cvmx_sli_mac_credit_cnt_s cnf71xx; 1715}; 1716 1717union cvmx_sli_mac_credit_cnt2 { 1718 uint64_t u64; 1719 struct cvmx_sli_mac_credit_cnt2_s { 1720#ifdef __BIG_ENDIAN_BITFIELD 1721 uint64_t reserved_54_63:10; 1722 uint64_t p3_c_d:1; 1723 uint64_t p3_n_d:1; 1724 uint64_t p3_p_d:1; 1725 uint64_t p2_c_d:1; 1726 uint64_t p2_n_d:1; 1727 uint64_t p2_p_d:1; 1728 uint64_t p3_ccnt:8; 1729 uint64_t p3_ncnt:8; 1730 uint64_t p3_pcnt:8; 1731 uint64_t p2_ccnt:8; 1732 uint64_t p2_ncnt:8; 1733 uint64_t p2_pcnt:8; 1734#else 1735 uint64_t p2_pcnt:8; 1736 uint64_t p2_ncnt:8; 1737 uint64_t p2_ccnt:8; 1738 uint64_t p3_pcnt:8; 1739 uint64_t p3_ncnt:8; 1740 uint64_t p3_ccnt:8; 1741 uint64_t p2_p_d:1; 1742 uint64_t p2_n_d:1; 1743 uint64_t p2_c_d:1; 1744 uint64_t p3_p_d:1; 1745 uint64_t p3_n_d:1; 1746 uint64_t p3_c_d:1; 1747 uint64_t reserved_54_63:10; 1748#endif 1749 } s; 1750 struct cvmx_sli_mac_credit_cnt2_s cn61xx; 1751 struct cvmx_sli_mac_credit_cnt2_s cn66xx; 1752 struct cvmx_sli_mac_credit_cnt2_s cnf71xx; 1753}; 1754 1755union cvmx_sli_mac_number { 1756 uint64_t u64; 1757 struct cvmx_sli_mac_number_s { 1758#ifdef __BIG_ENDIAN_BITFIELD 1759 uint64_t reserved_9_63:55; 1760 uint64_t a_mode:1; 1761 uint64_t num:8; 1762#else 1763 uint64_t num:8; 1764 uint64_t a_mode:1; 1765 uint64_t reserved_9_63:55; 1766#endif 1767 } s; 1768 struct cvmx_sli_mac_number_s cn61xx; 1769 struct cvmx_sli_mac_number_cn63xx { 1770#ifdef __BIG_ENDIAN_BITFIELD 1771 uint64_t reserved_8_63:56; 1772 uint64_t num:8; 1773#else 1774 uint64_t num:8; 1775 uint64_t reserved_8_63:56; 1776#endif 1777 } cn63xx; 1778 struct cvmx_sli_mac_number_s cn66xx; 1779 struct cvmx_sli_mac_number_cn63xx cn68xx; 1780 struct cvmx_sli_mac_number_cn63xx cn68xxp1; 1781 struct cvmx_sli_mac_number_s cnf71xx; 1782}; 1783 1784union cvmx_sli_mem_access_ctl { 1785 uint64_t u64; 1786 struct cvmx_sli_mem_access_ctl_s { 1787#ifdef __BIG_ENDIAN_BITFIELD 1788 uint64_t reserved_14_63:50; 1789 uint64_t max_word:4; 1790 uint64_t timer:10; 1791#else 1792 uint64_t timer:10; 1793 uint64_t max_word:4; 1794 uint64_t reserved_14_63:50; 1795#endif 1796 } s; 1797 struct cvmx_sli_mem_access_ctl_s cn61xx; 1798 struct cvmx_sli_mem_access_ctl_s cn63xx; 1799 struct cvmx_sli_mem_access_ctl_s cn63xxp1; 1800 struct cvmx_sli_mem_access_ctl_s cn66xx; 1801 struct cvmx_sli_mem_access_ctl_s cn68xx; 1802 struct cvmx_sli_mem_access_ctl_s cn68xxp1; 1803 struct cvmx_sli_mem_access_ctl_s cnf71xx; 1804}; 1805 1806union cvmx_sli_mem_access_subidx { 1807 uint64_t u64; 1808 struct cvmx_sli_mem_access_subidx_s { 1809#ifdef __BIG_ENDIAN_BITFIELD 1810 uint64_t reserved_43_63:21; 1811 uint64_t zero:1; 1812 uint64_t port:3; 1813 uint64_t nmerge:1; 1814 uint64_t esr:2; 1815 uint64_t esw:2; 1816 uint64_t wtype:2; 1817 uint64_t rtype:2; 1818 uint64_t reserved_0_29:30; 1819#else 1820 uint64_t reserved_0_29:30; 1821 uint64_t rtype:2; 1822 uint64_t wtype:2; 1823 uint64_t esw:2; 1824 uint64_t esr:2; 1825 uint64_t nmerge:1; 1826 uint64_t port:3; 1827 uint64_t zero:1; 1828 uint64_t reserved_43_63:21; 1829#endif 1830 } s; 1831 struct cvmx_sli_mem_access_subidx_cn61xx { 1832#ifdef __BIG_ENDIAN_BITFIELD 1833 uint64_t reserved_43_63:21; 1834 uint64_t zero:1; 1835 uint64_t port:3; 1836 uint64_t nmerge:1; 1837 uint64_t esr:2; 1838 uint64_t esw:2; 1839 uint64_t wtype:2; 1840 uint64_t rtype:2; 1841 uint64_t ba:30; 1842#else 1843 uint64_t ba:30; 1844 uint64_t rtype:2; 1845 uint64_t wtype:2; 1846 uint64_t esw:2; 1847 uint64_t esr:2; 1848 uint64_t nmerge:1; 1849 uint64_t port:3; 1850 uint64_t zero:1; 1851 uint64_t reserved_43_63:21; 1852#endif 1853 } cn61xx; 1854 struct cvmx_sli_mem_access_subidx_cn61xx cn63xx; 1855 struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1; 1856 struct cvmx_sli_mem_access_subidx_cn61xx cn66xx; 1857 struct cvmx_sli_mem_access_subidx_cn68xx { 1858#ifdef __BIG_ENDIAN_BITFIELD 1859 uint64_t reserved_43_63:21; 1860 uint64_t zero:1; 1861 uint64_t port:3; 1862 uint64_t nmerge:1; 1863 uint64_t esr:2; 1864 uint64_t esw:2; 1865 uint64_t wtype:2; 1866 uint64_t rtype:2; 1867 uint64_t ba:28; 1868 uint64_t reserved_0_1:2; 1869#else 1870 uint64_t reserved_0_1:2; 1871 uint64_t ba:28; 1872 uint64_t rtype:2; 1873 uint64_t wtype:2; 1874 uint64_t esw:2; 1875 uint64_t esr:2; 1876 uint64_t nmerge:1; 1877 uint64_t port:3; 1878 uint64_t zero:1; 1879 uint64_t reserved_43_63:21; 1880#endif 1881 } cn68xx; 1882 struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1; 1883 struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx; 1884}; 1885 1886union cvmx_sli_msi_enb0 { 1887 uint64_t u64; 1888 struct cvmx_sli_msi_enb0_s { 1889#ifdef __BIG_ENDIAN_BITFIELD 1890 uint64_t enb:64; 1891#else 1892 uint64_t enb:64; 1893#endif 1894 } s; 1895 struct cvmx_sli_msi_enb0_s cn61xx; 1896 struct cvmx_sli_msi_enb0_s cn63xx; 1897 struct cvmx_sli_msi_enb0_s cn63xxp1; 1898 struct cvmx_sli_msi_enb0_s cn66xx; 1899 struct cvmx_sli_msi_enb0_s cn68xx; 1900 struct cvmx_sli_msi_enb0_s cn68xxp1; 1901 struct cvmx_sli_msi_enb0_s cnf71xx; 1902}; 1903 1904union cvmx_sli_msi_enb1 { 1905 uint64_t u64; 1906 struct cvmx_sli_msi_enb1_s { 1907#ifdef __BIG_ENDIAN_BITFIELD 1908 uint64_t enb:64; 1909#else 1910 uint64_t enb:64; 1911#endif 1912 } s; 1913 struct cvmx_sli_msi_enb1_s cn61xx; 1914 struct cvmx_sli_msi_enb1_s cn63xx; 1915 struct cvmx_sli_msi_enb1_s cn63xxp1; 1916 struct cvmx_sli_msi_enb1_s cn66xx; 1917 struct cvmx_sli_msi_enb1_s cn68xx; 1918 struct cvmx_sli_msi_enb1_s cn68xxp1; 1919 struct cvmx_sli_msi_enb1_s cnf71xx; 1920}; 1921 1922union cvmx_sli_msi_enb2 { 1923 uint64_t u64; 1924 struct cvmx_sli_msi_enb2_s { 1925#ifdef __BIG_ENDIAN_BITFIELD 1926 uint64_t enb:64; 1927#else 1928 uint64_t enb:64; 1929#endif 1930 } s; 1931 struct cvmx_sli_msi_enb2_s cn61xx; 1932 struct cvmx_sli_msi_enb2_s cn63xx; 1933 struct cvmx_sli_msi_enb2_s cn63xxp1; 1934 struct cvmx_sli_msi_enb2_s cn66xx; 1935 struct cvmx_sli_msi_enb2_s cn68xx; 1936 struct cvmx_sli_msi_enb2_s cn68xxp1; 1937 struct cvmx_sli_msi_enb2_s cnf71xx; 1938}; 1939 1940union cvmx_sli_msi_enb3 { 1941 uint64_t u64; 1942 struct cvmx_sli_msi_enb3_s { 1943#ifdef __BIG_ENDIAN_BITFIELD 1944 uint64_t enb:64; 1945#else 1946 uint64_t enb:64; 1947#endif 1948 } s; 1949 struct cvmx_sli_msi_enb3_s cn61xx; 1950 struct cvmx_sli_msi_enb3_s cn63xx; 1951 struct cvmx_sli_msi_enb3_s cn63xxp1; 1952 struct cvmx_sli_msi_enb3_s cn66xx; 1953 struct cvmx_sli_msi_enb3_s cn68xx; 1954 struct cvmx_sli_msi_enb3_s cn68xxp1; 1955 struct cvmx_sli_msi_enb3_s cnf71xx; 1956}; 1957 1958union cvmx_sli_msi_rcv0 { 1959 uint64_t u64; 1960 struct cvmx_sli_msi_rcv0_s { 1961#ifdef __BIG_ENDIAN_BITFIELD 1962 uint64_t intr:64; 1963#else 1964 uint64_t intr:64; 1965#endif 1966 } s; 1967 struct cvmx_sli_msi_rcv0_s cn61xx; 1968 struct cvmx_sli_msi_rcv0_s cn63xx; 1969 struct cvmx_sli_msi_rcv0_s cn63xxp1; 1970 struct cvmx_sli_msi_rcv0_s cn66xx; 1971 struct cvmx_sli_msi_rcv0_s cn68xx; 1972 struct cvmx_sli_msi_rcv0_s cn68xxp1; 1973 struct cvmx_sli_msi_rcv0_s cnf71xx; 1974}; 1975 1976union cvmx_sli_msi_rcv1 { 1977 uint64_t u64; 1978 struct cvmx_sli_msi_rcv1_s { 1979#ifdef __BIG_ENDIAN_BITFIELD 1980 uint64_t intr:64; 1981#else 1982 uint64_t intr:64; 1983#endif 1984 } s; 1985 struct cvmx_sli_msi_rcv1_s cn61xx; 1986 struct cvmx_sli_msi_rcv1_s cn63xx; 1987 struct cvmx_sli_msi_rcv1_s cn63xxp1; 1988 struct cvmx_sli_msi_rcv1_s cn66xx; 1989 struct cvmx_sli_msi_rcv1_s cn68xx; 1990 struct cvmx_sli_msi_rcv1_s cn68xxp1; 1991 struct cvmx_sli_msi_rcv1_s cnf71xx; 1992}; 1993 1994union cvmx_sli_msi_rcv2 { 1995 uint64_t u64; 1996 struct cvmx_sli_msi_rcv2_s { 1997#ifdef __BIG_ENDIAN_BITFIELD 1998 uint64_t intr:64; 1999#else 2000 uint64_t intr:64; 2001#endif 2002 } s; 2003 struct cvmx_sli_msi_rcv2_s cn61xx; 2004 struct cvmx_sli_msi_rcv2_s cn63xx; 2005 struct cvmx_sli_msi_rcv2_s cn63xxp1; 2006 struct cvmx_sli_msi_rcv2_s cn66xx; 2007 struct cvmx_sli_msi_rcv2_s cn68xx; 2008 struct cvmx_sli_msi_rcv2_s cn68xxp1; 2009 struct cvmx_sli_msi_rcv2_s cnf71xx; 2010}; 2011 2012union cvmx_sli_msi_rcv3 { 2013 uint64_t u64; 2014 struct cvmx_sli_msi_rcv3_s { 2015#ifdef __BIG_ENDIAN_BITFIELD 2016 uint64_t intr:64; 2017#else 2018 uint64_t intr:64; 2019#endif 2020 } s; 2021 struct cvmx_sli_msi_rcv3_s cn61xx; 2022 struct cvmx_sli_msi_rcv3_s cn63xx; 2023 struct cvmx_sli_msi_rcv3_s cn63xxp1; 2024 struct cvmx_sli_msi_rcv3_s cn66xx; 2025 struct cvmx_sli_msi_rcv3_s cn68xx; 2026 struct cvmx_sli_msi_rcv3_s cn68xxp1; 2027 struct cvmx_sli_msi_rcv3_s cnf71xx; 2028}; 2029 2030union cvmx_sli_msi_rd_map { 2031 uint64_t u64; 2032 struct cvmx_sli_msi_rd_map_s { 2033#ifdef __BIG_ENDIAN_BITFIELD 2034 uint64_t reserved_16_63:48; 2035 uint64_t rd_int:8; 2036 uint64_t msi_int:8; 2037#else 2038 uint64_t msi_int:8; 2039 uint64_t rd_int:8; 2040 uint64_t reserved_16_63:48; 2041#endif 2042 } s; 2043 struct cvmx_sli_msi_rd_map_s cn61xx; 2044 struct cvmx_sli_msi_rd_map_s cn63xx; 2045 struct cvmx_sli_msi_rd_map_s cn63xxp1; 2046 struct cvmx_sli_msi_rd_map_s cn66xx; 2047 struct cvmx_sli_msi_rd_map_s cn68xx; 2048 struct cvmx_sli_msi_rd_map_s cn68xxp1; 2049 struct cvmx_sli_msi_rd_map_s cnf71xx; 2050}; 2051 2052union cvmx_sli_msi_w1c_enb0 { 2053 uint64_t u64; 2054 struct cvmx_sli_msi_w1c_enb0_s { 2055#ifdef __BIG_ENDIAN_BITFIELD 2056 uint64_t clr:64; 2057#else 2058 uint64_t clr:64; 2059#endif 2060 } s; 2061 struct cvmx_sli_msi_w1c_enb0_s cn61xx; 2062 struct cvmx_sli_msi_w1c_enb0_s cn63xx; 2063 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1; 2064 struct cvmx_sli_msi_w1c_enb0_s cn66xx; 2065 struct cvmx_sli_msi_w1c_enb0_s cn68xx; 2066 struct cvmx_sli_msi_w1c_enb0_s cn68xxp1; 2067 struct cvmx_sli_msi_w1c_enb0_s cnf71xx; 2068}; 2069 2070union cvmx_sli_msi_w1c_enb1 { 2071 uint64_t u64; 2072 struct cvmx_sli_msi_w1c_enb1_s { 2073#ifdef __BIG_ENDIAN_BITFIELD 2074 uint64_t clr:64; 2075#else 2076 uint64_t clr:64; 2077#endif 2078 } s; 2079 struct cvmx_sli_msi_w1c_enb1_s cn61xx; 2080 struct cvmx_sli_msi_w1c_enb1_s cn63xx; 2081 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1; 2082 struct cvmx_sli_msi_w1c_enb1_s cn66xx; 2083 struct cvmx_sli_msi_w1c_enb1_s cn68xx; 2084 struct cvmx_sli_msi_w1c_enb1_s cn68xxp1; 2085 struct cvmx_sli_msi_w1c_enb1_s cnf71xx; 2086}; 2087 2088union cvmx_sli_msi_w1c_enb2 { 2089 uint64_t u64; 2090 struct cvmx_sli_msi_w1c_enb2_s { 2091#ifdef __BIG_ENDIAN_BITFIELD 2092 uint64_t clr:64; 2093#else 2094 uint64_t clr:64; 2095#endif 2096 } s; 2097 struct cvmx_sli_msi_w1c_enb2_s cn61xx; 2098 struct cvmx_sli_msi_w1c_enb2_s cn63xx; 2099 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1; 2100 struct cvmx_sli_msi_w1c_enb2_s cn66xx; 2101 struct cvmx_sli_msi_w1c_enb2_s cn68xx; 2102 struct cvmx_sli_msi_w1c_enb2_s cn68xxp1; 2103 struct cvmx_sli_msi_w1c_enb2_s cnf71xx; 2104}; 2105 2106union cvmx_sli_msi_w1c_enb3 { 2107 uint64_t u64; 2108 struct cvmx_sli_msi_w1c_enb3_s { 2109#ifdef __BIG_ENDIAN_BITFIELD 2110 uint64_t clr:64; 2111#else 2112 uint64_t clr:64; 2113#endif 2114 } s; 2115 struct cvmx_sli_msi_w1c_enb3_s cn61xx; 2116 struct cvmx_sli_msi_w1c_enb3_s cn63xx; 2117 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1; 2118 struct cvmx_sli_msi_w1c_enb3_s cn66xx; 2119 struct cvmx_sli_msi_w1c_enb3_s cn68xx; 2120 struct cvmx_sli_msi_w1c_enb3_s cn68xxp1; 2121 struct cvmx_sli_msi_w1c_enb3_s cnf71xx; 2122}; 2123 2124union cvmx_sli_msi_w1s_enb0 { 2125 uint64_t u64; 2126 struct cvmx_sli_msi_w1s_enb0_s { 2127#ifdef __BIG_ENDIAN_BITFIELD 2128 uint64_t set:64; 2129#else 2130 uint64_t set:64; 2131#endif 2132 } s; 2133 struct cvmx_sli_msi_w1s_enb0_s cn61xx; 2134 struct cvmx_sli_msi_w1s_enb0_s cn63xx; 2135 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1; 2136 struct cvmx_sli_msi_w1s_enb0_s cn66xx; 2137 struct cvmx_sli_msi_w1s_enb0_s cn68xx; 2138 struct cvmx_sli_msi_w1s_enb0_s cn68xxp1; 2139 struct cvmx_sli_msi_w1s_enb0_s cnf71xx; 2140}; 2141 2142union cvmx_sli_msi_w1s_enb1 { 2143 uint64_t u64; 2144 struct cvmx_sli_msi_w1s_enb1_s { 2145#ifdef __BIG_ENDIAN_BITFIELD 2146 uint64_t set:64; 2147#else 2148 uint64_t set:64; 2149#endif 2150 } s; 2151 struct cvmx_sli_msi_w1s_enb1_s cn61xx; 2152 struct cvmx_sli_msi_w1s_enb1_s cn63xx; 2153 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1; 2154 struct cvmx_sli_msi_w1s_enb1_s cn66xx; 2155 struct cvmx_sli_msi_w1s_enb1_s cn68xx; 2156 struct cvmx_sli_msi_w1s_enb1_s cn68xxp1; 2157 struct cvmx_sli_msi_w1s_enb1_s cnf71xx; 2158}; 2159 2160union cvmx_sli_msi_w1s_enb2 { 2161 uint64_t u64; 2162 struct cvmx_sli_msi_w1s_enb2_s { 2163#ifdef __BIG_ENDIAN_BITFIELD 2164 uint64_t set:64; 2165#else 2166 uint64_t set:64; 2167#endif 2168 } s; 2169 struct cvmx_sli_msi_w1s_enb2_s cn61xx; 2170 struct cvmx_sli_msi_w1s_enb2_s cn63xx; 2171 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1; 2172 struct cvmx_sli_msi_w1s_enb2_s cn66xx; 2173 struct cvmx_sli_msi_w1s_enb2_s cn68xx; 2174 struct cvmx_sli_msi_w1s_enb2_s cn68xxp1; 2175 struct cvmx_sli_msi_w1s_enb2_s cnf71xx; 2176}; 2177 2178union cvmx_sli_msi_w1s_enb3 { 2179 uint64_t u64; 2180 struct cvmx_sli_msi_w1s_enb3_s { 2181#ifdef __BIG_ENDIAN_BITFIELD 2182 uint64_t set:64; 2183#else 2184 uint64_t set:64; 2185#endif 2186 } s; 2187 struct cvmx_sli_msi_w1s_enb3_s cn61xx; 2188 struct cvmx_sli_msi_w1s_enb3_s cn63xx; 2189 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1; 2190 struct cvmx_sli_msi_w1s_enb3_s cn66xx; 2191 struct cvmx_sli_msi_w1s_enb3_s cn68xx; 2192 struct cvmx_sli_msi_w1s_enb3_s cn68xxp1; 2193 struct cvmx_sli_msi_w1s_enb3_s cnf71xx; 2194}; 2195 2196union cvmx_sli_msi_wr_map { 2197 uint64_t u64; 2198 struct cvmx_sli_msi_wr_map_s { 2199#ifdef __BIG_ENDIAN_BITFIELD 2200 uint64_t reserved_16_63:48; 2201 uint64_t ciu_int:8; 2202 uint64_t msi_int:8; 2203#else 2204 uint64_t msi_int:8; 2205 uint64_t ciu_int:8; 2206 uint64_t reserved_16_63:48; 2207#endif 2208 } s; 2209 struct cvmx_sli_msi_wr_map_s cn61xx; 2210 struct cvmx_sli_msi_wr_map_s cn63xx; 2211 struct cvmx_sli_msi_wr_map_s cn63xxp1; 2212 struct cvmx_sli_msi_wr_map_s cn66xx; 2213 struct cvmx_sli_msi_wr_map_s cn68xx; 2214 struct cvmx_sli_msi_wr_map_s cn68xxp1; 2215 struct cvmx_sli_msi_wr_map_s cnf71xx; 2216}; 2217 2218union cvmx_sli_pcie_msi_rcv { 2219 uint64_t u64; 2220 struct cvmx_sli_pcie_msi_rcv_s { 2221#ifdef __BIG_ENDIAN_BITFIELD 2222 uint64_t reserved_8_63:56; 2223 uint64_t intr:8; 2224#else 2225 uint64_t intr:8; 2226 uint64_t reserved_8_63:56; 2227#endif 2228 } s; 2229 struct cvmx_sli_pcie_msi_rcv_s cn61xx; 2230 struct cvmx_sli_pcie_msi_rcv_s cn63xx; 2231 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1; 2232 struct cvmx_sli_pcie_msi_rcv_s cn66xx; 2233 struct cvmx_sli_pcie_msi_rcv_s cn68xx; 2234 struct cvmx_sli_pcie_msi_rcv_s cn68xxp1; 2235 struct cvmx_sli_pcie_msi_rcv_s cnf71xx; 2236}; 2237 2238union cvmx_sli_pcie_msi_rcv_b1 { 2239 uint64_t u64; 2240 struct cvmx_sli_pcie_msi_rcv_b1_s { 2241#ifdef __BIG_ENDIAN_BITFIELD 2242 uint64_t reserved_16_63:48; 2243 uint64_t intr:8; 2244 uint64_t reserved_0_7:8; 2245#else 2246 uint64_t reserved_0_7:8; 2247 uint64_t intr:8; 2248 uint64_t reserved_16_63:48; 2249#endif 2250 } s; 2251 struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx; 2252 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx; 2253 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1; 2254 struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx; 2255 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx; 2256 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1; 2257 struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx; 2258}; 2259 2260union cvmx_sli_pcie_msi_rcv_b2 { 2261 uint64_t u64; 2262 struct cvmx_sli_pcie_msi_rcv_b2_s { 2263#ifdef __BIG_ENDIAN_BITFIELD 2264 uint64_t reserved_24_63:40; 2265 uint64_t intr:8; 2266 uint64_t reserved_0_15:16; 2267#else 2268 uint64_t reserved_0_15:16; 2269 uint64_t intr:8; 2270 uint64_t reserved_24_63:40; 2271#endif 2272 } s; 2273 struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx; 2274 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx; 2275 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1; 2276 struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx; 2277 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx; 2278 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1; 2279 struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx; 2280}; 2281 2282union cvmx_sli_pcie_msi_rcv_b3 { 2283 uint64_t u64; 2284 struct cvmx_sli_pcie_msi_rcv_b3_s { 2285#ifdef __BIG_ENDIAN_BITFIELD 2286 uint64_t reserved_32_63:32; 2287 uint64_t intr:8; 2288 uint64_t reserved_0_23:24; 2289#else 2290 uint64_t reserved_0_23:24; 2291 uint64_t intr:8; 2292 uint64_t reserved_32_63:32; 2293#endif 2294 } s; 2295 struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx; 2296 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx; 2297 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1; 2298 struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx; 2299 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx; 2300 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1; 2301 struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx; 2302}; 2303 2304union cvmx_sli_pktx_cnts { 2305 uint64_t u64; 2306 struct cvmx_sli_pktx_cnts_s { 2307#ifdef __BIG_ENDIAN_BITFIELD 2308 uint64_t reserved_54_63:10; 2309 uint64_t timer:22; 2310 uint64_t cnt:32; 2311#else 2312 uint64_t cnt:32; 2313 uint64_t timer:22; 2314 uint64_t reserved_54_63:10; 2315#endif 2316 } s; 2317 struct cvmx_sli_pktx_cnts_s cn61xx; 2318 struct cvmx_sli_pktx_cnts_s cn63xx; 2319 struct cvmx_sli_pktx_cnts_s cn63xxp1; 2320 struct cvmx_sli_pktx_cnts_s cn66xx; 2321 struct cvmx_sli_pktx_cnts_s cn68xx; 2322 struct cvmx_sli_pktx_cnts_s cn68xxp1; 2323 struct cvmx_sli_pktx_cnts_s cnf71xx; 2324}; 2325 2326union cvmx_sli_pktx_in_bp { 2327 uint64_t u64; 2328 struct cvmx_sli_pktx_in_bp_s { 2329#ifdef __BIG_ENDIAN_BITFIELD 2330 uint64_t wmark:32; 2331 uint64_t cnt:32; 2332#else 2333 uint64_t cnt:32; 2334 uint64_t wmark:32; 2335#endif 2336 } s; 2337 struct cvmx_sli_pktx_in_bp_s cn61xx; 2338 struct cvmx_sli_pktx_in_bp_s cn63xx; 2339 struct cvmx_sli_pktx_in_bp_s cn63xxp1; 2340 struct cvmx_sli_pktx_in_bp_s cn66xx; 2341 struct cvmx_sli_pktx_in_bp_s cnf71xx; 2342}; 2343 2344union cvmx_sli_pktx_instr_baddr { 2345 uint64_t u64; 2346 struct cvmx_sli_pktx_instr_baddr_s { 2347#ifdef __BIG_ENDIAN_BITFIELD 2348 uint64_t addr:61; 2349 uint64_t reserved_0_2:3; 2350#else 2351 uint64_t reserved_0_2:3; 2352 uint64_t addr:61; 2353#endif 2354 } s; 2355 struct cvmx_sli_pktx_instr_baddr_s cn61xx; 2356 struct cvmx_sli_pktx_instr_baddr_s cn63xx; 2357 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1; 2358 struct cvmx_sli_pktx_instr_baddr_s cn66xx; 2359 struct cvmx_sli_pktx_instr_baddr_s cn68xx; 2360 struct cvmx_sli_pktx_instr_baddr_s cn68xxp1; 2361 struct cvmx_sli_pktx_instr_baddr_s cnf71xx; 2362}; 2363 2364union cvmx_sli_pktx_instr_baoff_dbell { 2365 uint64_t u64; 2366 struct cvmx_sli_pktx_instr_baoff_dbell_s { 2367#ifdef __BIG_ENDIAN_BITFIELD 2368 uint64_t aoff:32; 2369 uint64_t dbell:32; 2370#else 2371 uint64_t dbell:32; 2372 uint64_t aoff:32; 2373#endif 2374 } s; 2375 struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx; 2376 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx; 2377 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1; 2378 struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx; 2379 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx; 2380 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1; 2381 struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx; 2382}; 2383 2384union cvmx_sli_pktx_instr_fifo_rsize { 2385 uint64_t u64; 2386 struct cvmx_sli_pktx_instr_fifo_rsize_s { 2387#ifdef __BIG_ENDIAN_BITFIELD 2388 uint64_t max:9; 2389 uint64_t rrp:9; 2390 uint64_t wrp:9; 2391 uint64_t fcnt:5; 2392 uint64_t rsize:32; 2393#else 2394 uint64_t rsize:32; 2395 uint64_t fcnt:5; 2396 uint64_t wrp:9; 2397 uint64_t rrp:9; 2398 uint64_t max:9; 2399#endif 2400 } s; 2401 struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx; 2402 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx; 2403 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1; 2404 struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx; 2405 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx; 2406 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1; 2407 struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx; 2408}; 2409 2410union cvmx_sli_pktx_instr_header { 2411 uint64_t u64; 2412 struct cvmx_sli_pktx_instr_header_s { 2413#ifdef __BIG_ENDIAN_BITFIELD 2414 uint64_t reserved_44_63:20; 2415 uint64_t pbp:1; 2416 uint64_t reserved_38_42:5; 2417 uint64_t rparmode:2; 2418 uint64_t reserved_35_35:1; 2419 uint64_t rskp_len:7; 2420 uint64_t rngrpext:2; 2421 uint64_t rnqos:1; 2422 uint64_t rngrp:1; 2423 uint64_t rntt:1; 2424 uint64_t rntag:1; 2425 uint64_t use_ihdr:1; 2426 uint64_t reserved_16_20:5; 2427 uint64_t par_mode:2; 2428 uint64_t reserved_13_13:1; 2429 uint64_t skp_len:7; 2430 uint64_t ngrpext:2; 2431 uint64_t nqos:1; 2432 uint64_t ngrp:1; 2433 uint64_t ntt:1; 2434 uint64_t ntag:1; 2435#else 2436 uint64_t ntag:1; 2437 uint64_t ntt:1; 2438 uint64_t ngrp:1; 2439 uint64_t nqos:1; 2440 uint64_t ngrpext:2; 2441 uint64_t skp_len:7; 2442 uint64_t reserved_13_13:1; 2443 uint64_t par_mode:2; 2444 uint64_t reserved_16_20:5; 2445 uint64_t use_ihdr:1; 2446 uint64_t rntag:1; 2447 uint64_t rntt:1; 2448 uint64_t rngrp:1; 2449 uint64_t rnqos:1; 2450 uint64_t rngrpext:2; 2451 uint64_t rskp_len:7; 2452 uint64_t reserved_35_35:1; 2453 uint64_t rparmode:2; 2454 uint64_t reserved_38_42:5; 2455 uint64_t pbp:1; 2456 uint64_t reserved_44_63:20; 2457#endif 2458 } s; 2459 struct cvmx_sli_pktx_instr_header_cn61xx { 2460#ifdef __BIG_ENDIAN_BITFIELD 2461 uint64_t reserved_44_63:20; 2462 uint64_t pbp:1; 2463 uint64_t reserved_38_42:5; 2464 uint64_t rparmode:2; 2465 uint64_t reserved_35_35:1; 2466 uint64_t rskp_len:7; 2467 uint64_t reserved_26_27:2; 2468 uint64_t rnqos:1; 2469 uint64_t rngrp:1; 2470 uint64_t rntt:1; 2471 uint64_t rntag:1; 2472 uint64_t use_ihdr:1; 2473 uint64_t reserved_16_20:5; 2474 uint64_t par_mode:2; 2475 uint64_t reserved_13_13:1; 2476 uint64_t skp_len:7; 2477 uint64_t reserved_4_5:2; 2478 uint64_t nqos:1; 2479 uint64_t ngrp:1; 2480 uint64_t ntt:1; 2481 uint64_t ntag:1; 2482#else 2483 uint64_t ntag:1; 2484 uint64_t ntt:1; 2485 uint64_t ngrp:1; 2486 uint64_t nqos:1; 2487 uint64_t reserved_4_5:2; 2488 uint64_t skp_len:7; 2489 uint64_t reserved_13_13:1; 2490 uint64_t par_mode:2; 2491 uint64_t reserved_16_20:5; 2492 uint64_t use_ihdr:1; 2493 uint64_t rntag:1; 2494 uint64_t rntt:1; 2495 uint64_t rngrp:1; 2496 uint64_t rnqos:1; 2497 uint64_t reserved_26_27:2; 2498 uint64_t rskp_len:7; 2499 uint64_t reserved_35_35:1; 2500 uint64_t rparmode:2; 2501 uint64_t reserved_38_42:5; 2502 uint64_t pbp:1; 2503 uint64_t reserved_44_63:20; 2504#endif 2505 } cn61xx; 2506 struct cvmx_sli_pktx_instr_header_cn61xx cn63xx; 2507 struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1; 2508 struct cvmx_sli_pktx_instr_header_cn61xx cn66xx; 2509 struct cvmx_sli_pktx_instr_header_s cn68xx; 2510 struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1; 2511 struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx; 2512}; 2513 2514union cvmx_sli_pktx_out_size { 2515 uint64_t u64; 2516 struct cvmx_sli_pktx_out_size_s { 2517#ifdef __BIG_ENDIAN_BITFIELD 2518 uint64_t reserved_23_63:41; 2519 uint64_t isize:7; 2520 uint64_t bsize:16; 2521#else 2522 uint64_t bsize:16; 2523 uint64_t isize:7; 2524 uint64_t reserved_23_63:41; 2525#endif 2526 } s; 2527 struct cvmx_sli_pktx_out_size_s cn61xx; 2528 struct cvmx_sli_pktx_out_size_s cn63xx; 2529 struct cvmx_sli_pktx_out_size_s cn63xxp1; 2530 struct cvmx_sli_pktx_out_size_s cn66xx; 2531 struct cvmx_sli_pktx_out_size_s cn68xx; 2532 struct cvmx_sli_pktx_out_size_s cn68xxp1; 2533 struct cvmx_sli_pktx_out_size_s cnf71xx; 2534}; 2535 2536union cvmx_sli_pktx_slist_baddr { 2537 uint64_t u64; 2538 struct cvmx_sli_pktx_slist_baddr_s { 2539#ifdef __BIG_ENDIAN_BITFIELD 2540 uint64_t addr:60; 2541 uint64_t reserved_0_3:4; 2542#else 2543 uint64_t reserved_0_3:4; 2544 uint64_t addr:60; 2545#endif 2546 } s; 2547 struct cvmx_sli_pktx_slist_baddr_s cn61xx; 2548 struct cvmx_sli_pktx_slist_baddr_s cn63xx; 2549 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1; 2550 struct cvmx_sli_pktx_slist_baddr_s cn66xx; 2551 struct cvmx_sli_pktx_slist_baddr_s cn68xx; 2552 struct cvmx_sli_pktx_slist_baddr_s cn68xxp1; 2553 struct cvmx_sli_pktx_slist_baddr_s cnf71xx; 2554}; 2555 2556union cvmx_sli_pktx_slist_baoff_dbell { 2557 uint64_t u64; 2558 struct cvmx_sli_pktx_slist_baoff_dbell_s { 2559#ifdef __BIG_ENDIAN_BITFIELD 2560 uint64_t aoff:32; 2561 uint64_t dbell:32; 2562#else 2563 uint64_t dbell:32; 2564 uint64_t aoff:32; 2565#endif 2566 } s; 2567 struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx; 2568 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx; 2569 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1; 2570 struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx; 2571 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx; 2572 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1; 2573 struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx; 2574}; 2575 2576union cvmx_sli_pktx_slist_fifo_rsize { 2577 uint64_t u64; 2578 struct cvmx_sli_pktx_slist_fifo_rsize_s { 2579#ifdef __BIG_ENDIAN_BITFIELD 2580 uint64_t reserved_32_63:32; 2581 uint64_t rsize:32; 2582#else 2583 uint64_t rsize:32; 2584 uint64_t reserved_32_63:32; 2585#endif 2586 } s; 2587 struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx; 2588 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx; 2589 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1; 2590 struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx; 2591 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx; 2592 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1; 2593 struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx; 2594}; 2595 2596union cvmx_sli_pkt_cnt_int { 2597 uint64_t u64; 2598 struct cvmx_sli_pkt_cnt_int_s { 2599#ifdef __BIG_ENDIAN_BITFIELD 2600 uint64_t reserved_32_63:32; 2601 uint64_t port:32; 2602#else 2603 uint64_t port:32; 2604 uint64_t reserved_32_63:32; 2605#endif 2606 } s; 2607 struct cvmx_sli_pkt_cnt_int_s cn61xx; 2608 struct cvmx_sli_pkt_cnt_int_s cn63xx; 2609 struct cvmx_sli_pkt_cnt_int_s cn63xxp1; 2610 struct cvmx_sli_pkt_cnt_int_s cn66xx; 2611 struct cvmx_sli_pkt_cnt_int_s cn68xx; 2612 struct cvmx_sli_pkt_cnt_int_s cn68xxp1; 2613 struct cvmx_sli_pkt_cnt_int_s cnf71xx; 2614}; 2615 2616union cvmx_sli_pkt_cnt_int_enb { 2617 uint64_t u64; 2618 struct cvmx_sli_pkt_cnt_int_enb_s { 2619#ifdef __BIG_ENDIAN_BITFIELD 2620 uint64_t reserved_32_63:32; 2621 uint64_t port:32; 2622#else 2623 uint64_t port:32; 2624 uint64_t reserved_32_63:32; 2625#endif 2626 } s; 2627 struct cvmx_sli_pkt_cnt_int_enb_s cn61xx; 2628 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx; 2629 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1; 2630 struct cvmx_sli_pkt_cnt_int_enb_s cn66xx; 2631 struct cvmx_sli_pkt_cnt_int_enb_s cn68xx; 2632 struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1; 2633 struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx; 2634}; 2635 2636union cvmx_sli_pkt_ctl { 2637 uint64_t u64; 2638 struct cvmx_sli_pkt_ctl_s { 2639#ifdef __BIG_ENDIAN_BITFIELD 2640 uint64_t reserved_5_63:59; 2641 uint64_t ring_en:1; 2642 uint64_t pkt_bp:4; 2643#else 2644 uint64_t pkt_bp:4; 2645 uint64_t ring_en:1; 2646 uint64_t reserved_5_63:59; 2647#endif 2648 } s; 2649 struct cvmx_sli_pkt_ctl_s cn61xx; 2650 struct cvmx_sli_pkt_ctl_s cn63xx; 2651 struct cvmx_sli_pkt_ctl_s cn63xxp1; 2652 struct cvmx_sli_pkt_ctl_s cn66xx; 2653 struct cvmx_sli_pkt_ctl_s cn68xx; 2654 struct cvmx_sli_pkt_ctl_s cn68xxp1; 2655 struct cvmx_sli_pkt_ctl_s cnf71xx; 2656}; 2657 2658union cvmx_sli_pkt_data_out_es { 2659 uint64_t u64; 2660 struct cvmx_sli_pkt_data_out_es_s { 2661#ifdef __BIG_ENDIAN_BITFIELD 2662 uint64_t es:64; 2663#else 2664 uint64_t es:64; 2665#endif 2666 } s; 2667 struct cvmx_sli_pkt_data_out_es_s cn61xx; 2668 struct cvmx_sli_pkt_data_out_es_s cn63xx; 2669 struct cvmx_sli_pkt_data_out_es_s cn63xxp1; 2670 struct cvmx_sli_pkt_data_out_es_s cn66xx; 2671 struct cvmx_sli_pkt_data_out_es_s cn68xx; 2672 struct cvmx_sli_pkt_data_out_es_s cn68xxp1; 2673 struct cvmx_sli_pkt_data_out_es_s cnf71xx; 2674}; 2675 2676union cvmx_sli_pkt_data_out_ns { 2677 uint64_t u64; 2678 struct cvmx_sli_pkt_data_out_ns_s { 2679#ifdef __BIG_ENDIAN_BITFIELD 2680 uint64_t reserved_32_63:32; 2681 uint64_t nsr:32; 2682#else 2683 uint64_t nsr:32; 2684 uint64_t reserved_32_63:32; 2685#endif 2686 } s; 2687 struct cvmx_sli_pkt_data_out_ns_s cn61xx; 2688 struct cvmx_sli_pkt_data_out_ns_s cn63xx; 2689 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1; 2690 struct cvmx_sli_pkt_data_out_ns_s cn66xx; 2691 struct cvmx_sli_pkt_data_out_ns_s cn68xx; 2692 struct cvmx_sli_pkt_data_out_ns_s cn68xxp1; 2693 struct cvmx_sli_pkt_data_out_ns_s cnf71xx; 2694}; 2695 2696union cvmx_sli_pkt_data_out_ror { 2697 uint64_t u64; 2698 struct cvmx_sli_pkt_data_out_ror_s { 2699#ifdef __BIG_ENDIAN_BITFIELD 2700 uint64_t reserved_32_63:32; 2701 uint64_t ror:32; 2702#else 2703 uint64_t ror:32; 2704 uint64_t reserved_32_63:32; 2705#endif 2706 } s; 2707 struct cvmx_sli_pkt_data_out_ror_s cn61xx; 2708 struct cvmx_sli_pkt_data_out_ror_s cn63xx; 2709 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1; 2710 struct cvmx_sli_pkt_data_out_ror_s cn66xx; 2711 struct cvmx_sli_pkt_data_out_ror_s cn68xx; 2712 struct cvmx_sli_pkt_data_out_ror_s cn68xxp1; 2713 struct cvmx_sli_pkt_data_out_ror_s cnf71xx; 2714}; 2715 2716union cvmx_sli_pkt_dpaddr { 2717 uint64_t u64; 2718 struct cvmx_sli_pkt_dpaddr_s { 2719#ifdef __BIG_ENDIAN_BITFIELD 2720 uint64_t reserved_32_63:32; 2721 uint64_t dptr:32; 2722#else 2723 uint64_t dptr:32; 2724 uint64_t reserved_32_63:32; 2725#endif 2726 } s; 2727 struct cvmx_sli_pkt_dpaddr_s cn61xx; 2728 struct cvmx_sli_pkt_dpaddr_s cn63xx; 2729 struct cvmx_sli_pkt_dpaddr_s cn63xxp1; 2730 struct cvmx_sli_pkt_dpaddr_s cn66xx; 2731 struct cvmx_sli_pkt_dpaddr_s cn68xx; 2732 struct cvmx_sli_pkt_dpaddr_s cn68xxp1; 2733 struct cvmx_sli_pkt_dpaddr_s cnf71xx; 2734}; 2735 2736union cvmx_sli_pkt_in_bp { 2737 uint64_t u64; 2738 struct cvmx_sli_pkt_in_bp_s { 2739#ifdef __BIG_ENDIAN_BITFIELD 2740 uint64_t reserved_32_63:32; 2741 uint64_t bp:32; 2742#else 2743 uint64_t bp:32; 2744 uint64_t reserved_32_63:32; 2745#endif 2746 } s; 2747 struct cvmx_sli_pkt_in_bp_s cn61xx; 2748 struct cvmx_sli_pkt_in_bp_s cn63xx; 2749 struct cvmx_sli_pkt_in_bp_s cn63xxp1; 2750 struct cvmx_sli_pkt_in_bp_s cn66xx; 2751 struct cvmx_sli_pkt_in_bp_s cnf71xx; 2752}; 2753 2754union cvmx_sli_pkt_in_donex_cnts { 2755 uint64_t u64; 2756 struct cvmx_sli_pkt_in_donex_cnts_s { 2757#ifdef __BIG_ENDIAN_BITFIELD 2758 uint64_t reserved_32_63:32; 2759 uint64_t cnt:32; 2760#else 2761 uint64_t cnt:32; 2762 uint64_t reserved_32_63:32; 2763#endif 2764 } s; 2765 struct cvmx_sli_pkt_in_donex_cnts_s cn61xx; 2766 struct cvmx_sli_pkt_in_donex_cnts_s cn63xx; 2767 struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1; 2768 struct cvmx_sli_pkt_in_donex_cnts_s cn66xx; 2769 struct cvmx_sli_pkt_in_donex_cnts_s cn68xx; 2770 struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1; 2771 struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx; 2772}; 2773 2774union cvmx_sli_pkt_in_instr_counts { 2775 uint64_t u64; 2776 struct cvmx_sli_pkt_in_instr_counts_s { 2777#ifdef __BIG_ENDIAN_BITFIELD 2778 uint64_t wr_cnt:32; 2779 uint64_t rd_cnt:32; 2780#else 2781 uint64_t rd_cnt:32; 2782 uint64_t wr_cnt:32; 2783#endif 2784 } s; 2785 struct cvmx_sli_pkt_in_instr_counts_s cn61xx; 2786 struct cvmx_sli_pkt_in_instr_counts_s cn63xx; 2787 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1; 2788 struct cvmx_sli_pkt_in_instr_counts_s cn66xx; 2789 struct cvmx_sli_pkt_in_instr_counts_s cn68xx; 2790 struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1; 2791 struct cvmx_sli_pkt_in_instr_counts_s cnf71xx; 2792}; 2793 2794union cvmx_sli_pkt_in_pcie_port { 2795 uint64_t u64; 2796 struct cvmx_sli_pkt_in_pcie_port_s { 2797#ifdef __BIG_ENDIAN_BITFIELD 2798 uint64_t pp:64; 2799#else 2800 uint64_t pp:64; 2801#endif 2802 } s; 2803 struct cvmx_sli_pkt_in_pcie_port_s cn61xx; 2804 struct cvmx_sli_pkt_in_pcie_port_s cn63xx; 2805 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1; 2806 struct cvmx_sli_pkt_in_pcie_port_s cn66xx; 2807 struct cvmx_sli_pkt_in_pcie_port_s cn68xx; 2808 struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1; 2809 struct cvmx_sli_pkt_in_pcie_port_s cnf71xx; 2810}; 2811 2812union cvmx_sli_pkt_input_control { 2813 uint64_t u64; 2814 struct cvmx_sli_pkt_input_control_s { 2815#ifdef __BIG_ENDIAN_BITFIELD 2816 uint64_t prd_erst:1; 2817 uint64_t prd_rds:7; 2818 uint64_t gii_erst:1; 2819 uint64_t gii_rds:7; 2820 uint64_t reserved_41_47:7; 2821 uint64_t prc_idle:1; 2822 uint64_t reserved_24_39:16; 2823 uint64_t pin_rst:1; 2824 uint64_t pkt_rr:1; 2825 uint64_t pbp_dhi:13; 2826 uint64_t d_nsr:1; 2827 uint64_t d_esr:2; 2828 uint64_t d_ror:1; 2829 uint64_t use_csr:1; 2830 uint64_t nsr:1; 2831 uint64_t esr:2; 2832 uint64_t ror:1; 2833#else 2834 uint64_t ror:1; 2835 uint64_t esr:2; 2836 uint64_t nsr:1; 2837 uint64_t use_csr:1; 2838 uint64_t d_ror:1; 2839 uint64_t d_esr:2; 2840 uint64_t d_nsr:1; 2841 uint64_t pbp_dhi:13; 2842 uint64_t pkt_rr:1; 2843 uint64_t pin_rst:1; 2844 uint64_t reserved_24_39:16; 2845 uint64_t prc_idle:1; 2846 uint64_t reserved_41_47:7; 2847 uint64_t gii_rds:7; 2848 uint64_t gii_erst:1; 2849 uint64_t prd_rds:7; 2850 uint64_t prd_erst:1; 2851#endif 2852 } s; 2853 struct cvmx_sli_pkt_input_control_s cn61xx; 2854 struct cvmx_sli_pkt_input_control_cn63xx { 2855#ifdef __BIG_ENDIAN_BITFIELD 2856 uint64_t reserved_23_63:41; 2857 uint64_t pkt_rr:1; 2858 uint64_t pbp_dhi:13; 2859 uint64_t d_nsr:1; 2860 uint64_t d_esr:2; 2861 uint64_t d_ror:1; 2862 uint64_t use_csr:1; 2863 uint64_t nsr:1; 2864 uint64_t esr:2; 2865 uint64_t ror:1; 2866#else 2867 uint64_t ror:1; 2868 uint64_t esr:2; 2869 uint64_t nsr:1; 2870 uint64_t use_csr:1; 2871 uint64_t d_ror:1; 2872 uint64_t d_esr:2; 2873 uint64_t d_nsr:1; 2874 uint64_t pbp_dhi:13; 2875 uint64_t pkt_rr:1; 2876 uint64_t reserved_23_63:41; 2877#endif 2878 } cn63xx; 2879 struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1; 2880 struct cvmx_sli_pkt_input_control_s cn66xx; 2881 struct cvmx_sli_pkt_input_control_s cn68xx; 2882 struct cvmx_sli_pkt_input_control_s cn68xxp1; 2883 struct cvmx_sli_pkt_input_control_s cnf71xx; 2884}; 2885 2886union cvmx_sli_pkt_instr_enb { 2887 uint64_t u64; 2888 struct cvmx_sli_pkt_instr_enb_s { 2889#ifdef __BIG_ENDIAN_BITFIELD 2890 uint64_t reserved_32_63:32; 2891 uint64_t enb:32; 2892#else 2893 uint64_t enb:32; 2894 uint64_t reserved_32_63:32; 2895#endif 2896 } s; 2897 struct cvmx_sli_pkt_instr_enb_s cn61xx; 2898 struct cvmx_sli_pkt_instr_enb_s cn63xx; 2899 struct cvmx_sli_pkt_instr_enb_s cn63xxp1; 2900 struct cvmx_sli_pkt_instr_enb_s cn66xx; 2901 struct cvmx_sli_pkt_instr_enb_s cn68xx; 2902 struct cvmx_sli_pkt_instr_enb_s cn68xxp1; 2903 struct cvmx_sli_pkt_instr_enb_s cnf71xx; 2904}; 2905 2906union cvmx_sli_pkt_instr_rd_size { 2907 uint64_t u64; 2908 struct cvmx_sli_pkt_instr_rd_size_s { 2909#ifdef __BIG_ENDIAN_BITFIELD 2910 uint64_t rdsize:64; 2911#else 2912 uint64_t rdsize:64; 2913#endif 2914 } s; 2915 struct cvmx_sli_pkt_instr_rd_size_s cn61xx; 2916 struct cvmx_sli_pkt_instr_rd_size_s cn63xx; 2917 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1; 2918 struct cvmx_sli_pkt_instr_rd_size_s cn66xx; 2919 struct cvmx_sli_pkt_instr_rd_size_s cn68xx; 2920 struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1; 2921 struct cvmx_sli_pkt_instr_rd_size_s cnf71xx; 2922}; 2923 2924union cvmx_sli_pkt_instr_size { 2925 uint64_t u64; 2926 struct cvmx_sli_pkt_instr_size_s { 2927#ifdef __BIG_ENDIAN_BITFIELD 2928 uint64_t reserved_32_63:32; 2929 uint64_t is_64b:32; 2930#else 2931 uint64_t is_64b:32; 2932 uint64_t reserved_32_63:32; 2933#endif 2934 } s; 2935 struct cvmx_sli_pkt_instr_size_s cn61xx; 2936 struct cvmx_sli_pkt_instr_size_s cn63xx; 2937 struct cvmx_sli_pkt_instr_size_s cn63xxp1; 2938 struct cvmx_sli_pkt_instr_size_s cn66xx; 2939 struct cvmx_sli_pkt_instr_size_s cn68xx; 2940 struct cvmx_sli_pkt_instr_size_s cn68xxp1; 2941 struct cvmx_sli_pkt_instr_size_s cnf71xx; 2942}; 2943 2944union cvmx_sli_pkt_int_levels { 2945 uint64_t u64; 2946 struct cvmx_sli_pkt_int_levels_s { 2947#ifdef __BIG_ENDIAN_BITFIELD 2948 uint64_t reserved_54_63:10; 2949 uint64_t time:22; 2950 uint64_t cnt:32; 2951#else 2952 uint64_t cnt:32; 2953 uint64_t time:22; 2954 uint64_t reserved_54_63:10; 2955#endif 2956 } s; 2957 struct cvmx_sli_pkt_int_levels_s cn61xx; 2958 struct cvmx_sli_pkt_int_levels_s cn63xx; 2959 struct cvmx_sli_pkt_int_levels_s cn63xxp1; 2960 struct cvmx_sli_pkt_int_levels_s cn66xx; 2961 struct cvmx_sli_pkt_int_levels_s cn68xx; 2962 struct cvmx_sli_pkt_int_levels_s cn68xxp1; 2963 struct cvmx_sli_pkt_int_levels_s cnf71xx; 2964}; 2965 2966union cvmx_sli_pkt_iptr { 2967 uint64_t u64; 2968 struct cvmx_sli_pkt_iptr_s { 2969#ifdef __BIG_ENDIAN_BITFIELD 2970 uint64_t reserved_32_63:32; 2971 uint64_t iptr:32; 2972#else 2973 uint64_t iptr:32; 2974 uint64_t reserved_32_63:32; 2975#endif 2976 } s; 2977 struct cvmx_sli_pkt_iptr_s cn61xx; 2978 struct cvmx_sli_pkt_iptr_s cn63xx; 2979 struct cvmx_sli_pkt_iptr_s cn63xxp1; 2980 struct cvmx_sli_pkt_iptr_s cn66xx; 2981 struct cvmx_sli_pkt_iptr_s cn68xx; 2982 struct cvmx_sli_pkt_iptr_s cn68xxp1; 2983 struct cvmx_sli_pkt_iptr_s cnf71xx; 2984}; 2985 2986union cvmx_sli_pkt_out_bmode { 2987 uint64_t u64; 2988 struct cvmx_sli_pkt_out_bmode_s { 2989#ifdef __BIG_ENDIAN_BITFIELD 2990 uint64_t reserved_32_63:32; 2991 uint64_t bmode:32; 2992#else 2993 uint64_t bmode:32; 2994 uint64_t reserved_32_63:32; 2995#endif 2996 } s; 2997 struct cvmx_sli_pkt_out_bmode_s cn61xx; 2998 struct cvmx_sli_pkt_out_bmode_s cn63xx; 2999 struct cvmx_sli_pkt_out_bmode_s cn63xxp1; 3000 struct cvmx_sli_pkt_out_bmode_s cn66xx; 3001 struct cvmx_sli_pkt_out_bmode_s cn68xx; 3002 struct cvmx_sli_pkt_out_bmode_s cn68xxp1; 3003 struct cvmx_sli_pkt_out_bmode_s cnf71xx; 3004}; 3005 3006union cvmx_sli_pkt_out_bp_en { 3007 uint64_t u64; 3008 struct cvmx_sli_pkt_out_bp_en_s { 3009#ifdef __BIG_ENDIAN_BITFIELD 3010 uint64_t reserved_32_63:32; 3011 uint64_t bp_en:32; 3012#else 3013 uint64_t bp_en:32; 3014 uint64_t reserved_32_63:32; 3015#endif 3016 } s; 3017 struct cvmx_sli_pkt_out_bp_en_s cn68xx; 3018 struct cvmx_sli_pkt_out_bp_en_s cn68xxp1; 3019}; 3020 3021union cvmx_sli_pkt_out_enb { 3022 uint64_t u64; 3023 struct cvmx_sli_pkt_out_enb_s { 3024#ifdef __BIG_ENDIAN_BITFIELD 3025 uint64_t reserved_32_63:32; 3026 uint64_t enb:32; 3027#else 3028 uint64_t enb:32; 3029 uint64_t reserved_32_63:32; 3030#endif 3031 } s; 3032 struct cvmx_sli_pkt_out_enb_s cn61xx; 3033 struct cvmx_sli_pkt_out_enb_s cn63xx; 3034 struct cvmx_sli_pkt_out_enb_s cn63xxp1; 3035 struct cvmx_sli_pkt_out_enb_s cn66xx; 3036 struct cvmx_sli_pkt_out_enb_s cn68xx; 3037 struct cvmx_sli_pkt_out_enb_s cn68xxp1; 3038 struct cvmx_sli_pkt_out_enb_s cnf71xx; 3039}; 3040 3041union cvmx_sli_pkt_output_wmark { 3042 uint64_t u64; 3043 struct cvmx_sli_pkt_output_wmark_s { 3044#ifdef __BIG_ENDIAN_BITFIELD 3045 uint64_t reserved_32_63:32; 3046 uint64_t wmark:32; 3047#else 3048 uint64_t wmark:32; 3049 uint64_t reserved_32_63:32; 3050#endif 3051 } s; 3052 struct cvmx_sli_pkt_output_wmark_s cn61xx; 3053 struct cvmx_sli_pkt_output_wmark_s cn63xx; 3054 struct cvmx_sli_pkt_output_wmark_s cn63xxp1; 3055 struct cvmx_sli_pkt_output_wmark_s cn66xx; 3056 struct cvmx_sli_pkt_output_wmark_s cn68xx; 3057 struct cvmx_sli_pkt_output_wmark_s cn68xxp1; 3058 struct cvmx_sli_pkt_output_wmark_s cnf71xx; 3059}; 3060 3061union cvmx_sli_pkt_pcie_port { 3062 uint64_t u64; 3063 struct cvmx_sli_pkt_pcie_port_s { 3064#ifdef __BIG_ENDIAN_BITFIELD 3065 uint64_t pp:64; 3066#else 3067 uint64_t pp:64; 3068#endif 3069 } s; 3070 struct cvmx_sli_pkt_pcie_port_s cn61xx; 3071 struct cvmx_sli_pkt_pcie_port_s cn63xx; 3072 struct cvmx_sli_pkt_pcie_port_s cn63xxp1; 3073 struct cvmx_sli_pkt_pcie_port_s cn66xx; 3074 struct cvmx_sli_pkt_pcie_port_s cn68xx; 3075 struct cvmx_sli_pkt_pcie_port_s cn68xxp1; 3076 struct cvmx_sli_pkt_pcie_port_s cnf71xx; 3077}; 3078 3079union cvmx_sli_pkt_port_in_rst { 3080 uint64_t u64; 3081 struct cvmx_sli_pkt_port_in_rst_s { 3082#ifdef __BIG_ENDIAN_BITFIELD 3083 uint64_t in_rst:32; 3084 uint64_t out_rst:32; 3085#else 3086 uint64_t out_rst:32; 3087 uint64_t in_rst:32; 3088#endif 3089 } s; 3090 struct cvmx_sli_pkt_port_in_rst_s cn61xx; 3091 struct cvmx_sli_pkt_port_in_rst_s cn63xx; 3092 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1; 3093 struct cvmx_sli_pkt_port_in_rst_s cn66xx; 3094 struct cvmx_sli_pkt_port_in_rst_s cn68xx; 3095 struct cvmx_sli_pkt_port_in_rst_s cn68xxp1; 3096 struct cvmx_sli_pkt_port_in_rst_s cnf71xx; 3097}; 3098 3099union cvmx_sli_pkt_slist_es { 3100 uint64_t u64; 3101 struct cvmx_sli_pkt_slist_es_s { 3102#ifdef __BIG_ENDIAN_BITFIELD 3103 uint64_t es:64; 3104#else 3105 uint64_t es:64; 3106#endif 3107 } s; 3108 struct cvmx_sli_pkt_slist_es_s cn61xx; 3109 struct cvmx_sli_pkt_slist_es_s cn63xx; 3110 struct cvmx_sli_pkt_slist_es_s cn63xxp1; 3111 struct cvmx_sli_pkt_slist_es_s cn66xx; 3112 struct cvmx_sli_pkt_slist_es_s cn68xx; 3113 struct cvmx_sli_pkt_slist_es_s cn68xxp1; 3114 struct cvmx_sli_pkt_slist_es_s cnf71xx; 3115}; 3116 3117union cvmx_sli_pkt_slist_ns { 3118 uint64_t u64; 3119 struct cvmx_sli_pkt_slist_ns_s { 3120#ifdef __BIG_ENDIAN_BITFIELD 3121 uint64_t reserved_32_63:32; 3122 uint64_t nsr:32; 3123#else 3124 uint64_t nsr:32; 3125 uint64_t reserved_32_63:32; 3126#endif 3127 } s; 3128 struct cvmx_sli_pkt_slist_ns_s cn61xx; 3129 struct cvmx_sli_pkt_slist_ns_s cn63xx; 3130 struct cvmx_sli_pkt_slist_ns_s cn63xxp1; 3131 struct cvmx_sli_pkt_slist_ns_s cn66xx; 3132 struct cvmx_sli_pkt_slist_ns_s cn68xx; 3133 struct cvmx_sli_pkt_slist_ns_s cn68xxp1; 3134 struct cvmx_sli_pkt_slist_ns_s cnf71xx; 3135}; 3136 3137union cvmx_sli_pkt_slist_ror { 3138 uint64_t u64; 3139 struct cvmx_sli_pkt_slist_ror_s { 3140#ifdef __BIG_ENDIAN_BITFIELD 3141 uint64_t reserved_32_63:32; 3142 uint64_t ror:32; 3143#else 3144 uint64_t ror:32; 3145 uint64_t reserved_32_63:32; 3146#endif 3147 } s; 3148 struct cvmx_sli_pkt_slist_ror_s cn61xx; 3149 struct cvmx_sli_pkt_slist_ror_s cn63xx; 3150 struct cvmx_sli_pkt_slist_ror_s cn63xxp1; 3151 struct cvmx_sli_pkt_slist_ror_s cn66xx; 3152 struct cvmx_sli_pkt_slist_ror_s cn68xx; 3153 struct cvmx_sli_pkt_slist_ror_s cn68xxp1; 3154 struct cvmx_sli_pkt_slist_ror_s cnf71xx; 3155}; 3156 3157union cvmx_sli_pkt_time_int { 3158 uint64_t u64; 3159 struct cvmx_sli_pkt_time_int_s { 3160#ifdef __BIG_ENDIAN_BITFIELD 3161 uint64_t reserved_32_63:32; 3162 uint64_t port:32; 3163#else 3164 uint64_t port:32; 3165 uint64_t reserved_32_63:32; 3166#endif 3167 } s; 3168 struct cvmx_sli_pkt_time_int_s cn61xx; 3169 struct cvmx_sli_pkt_time_int_s cn63xx; 3170 struct cvmx_sli_pkt_time_int_s cn63xxp1; 3171 struct cvmx_sli_pkt_time_int_s cn66xx; 3172 struct cvmx_sli_pkt_time_int_s cn68xx; 3173 struct cvmx_sli_pkt_time_int_s cn68xxp1; 3174 struct cvmx_sli_pkt_time_int_s cnf71xx; 3175}; 3176 3177union cvmx_sli_pkt_time_int_enb { 3178 uint64_t u64; 3179 struct cvmx_sli_pkt_time_int_enb_s { 3180#ifdef __BIG_ENDIAN_BITFIELD 3181 uint64_t reserved_32_63:32; 3182 uint64_t port:32; 3183#else 3184 uint64_t port:32; 3185 uint64_t reserved_32_63:32; 3186#endif 3187 } s; 3188 struct cvmx_sli_pkt_time_int_enb_s cn61xx; 3189 struct cvmx_sli_pkt_time_int_enb_s cn63xx; 3190 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1; 3191 struct cvmx_sli_pkt_time_int_enb_s cn66xx; 3192 struct cvmx_sli_pkt_time_int_enb_s cn68xx; 3193 struct cvmx_sli_pkt_time_int_enb_s cn68xxp1; 3194 struct cvmx_sli_pkt_time_int_enb_s cnf71xx; 3195}; 3196 3197union cvmx_sli_portx_pkind { 3198 uint64_t u64; 3199 struct cvmx_sli_portx_pkind_s { 3200#ifdef __BIG_ENDIAN_BITFIELD 3201 uint64_t reserved_25_63:39; 3202 uint64_t rpk_enb:1; 3203 uint64_t reserved_22_23:2; 3204 uint64_t pkindr:6; 3205 uint64_t reserved_14_15:2; 3206 uint64_t bpkind:6; 3207 uint64_t reserved_6_7:2; 3208 uint64_t pkind:6; 3209#else 3210 uint64_t pkind:6; 3211 uint64_t reserved_6_7:2; 3212 uint64_t bpkind:6; 3213 uint64_t reserved_14_15:2; 3214 uint64_t pkindr:6; 3215 uint64_t reserved_22_23:2; 3216 uint64_t rpk_enb:1; 3217 uint64_t reserved_25_63:39; 3218#endif 3219 } s; 3220 struct cvmx_sli_portx_pkind_s cn68xx; 3221 struct cvmx_sli_portx_pkind_cn68xxp1 { 3222#ifdef __BIG_ENDIAN_BITFIELD 3223 uint64_t reserved_14_63:50; 3224 uint64_t bpkind:6; 3225 uint64_t reserved_6_7:2; 3226 uint64_t pkind:6; 3227#else 3228 uint64_t pkind:6; 3229 uint64_t reserved_6_7:2; 3230 uint64_t bpkind:6; 3231 uint64_t reserved_14_63:50; 3232#endif 3233 } cn68xxp1; 3234}; 3235 3236union cvmx_sli_s2m_portx_ctl { 3237 uint64_t u64; 3238 struct cvmx_sli_s2m_portx_ctl_s { 3239#ifdef __BIG_ENDIAN_BITFIELD 3240 uint64_t reserved_5_63:59; 3241 uint64_t wind_d:1; 3242 uint64_t bar0_d:1; 3243 uint64_t mrrs:3; 3244#else 3245 uint64_t mrrs:3; 3246 uint64_t bar0_d:1; 3247 uint64_t wind_d:1; 3248 uint64_t reserved_5_63:59; 3249#endif 3250 } s; 3251 struct cvmx_sli_s2m_portx_ctl_s cn61xx; 3252 struct cvmx_sli_s2m_portx_ctl_s cn63xx; 3253 struct cvmx_sli_s2m_portx_ctl_s cn63xxp1; 3254 struct cvmx_sli_s2m_portx_ctl_s cn66xx; 3255 struct cvmx_sli_s2m_portx_ctl_s cn68xx; 3256 struct cvmx_sli_s2m_portx_ctl_s cn68xxp1; 3257 struct cvmx_sli_s2m_portx_ctl_s cnf71xx; 3258}; 3259 3260union cvmx_sli_scratch_1 { 3261 uint64_t u64; 3262 struct cvmx_sli_scratch_1_s { 3263#ifdef __BIG_ENDIAN_BITFIELD 3264 uint64_t data:64; 3265#else 3266 uint64_t data:64; 3267#endif 3268 } s; 3269 struct cvmx_sli_scratch_1_s cn61xx; 3270 struct cvmx_sli_scratch_1_s cn63xx; 3271 struct cvmx_sli_scratch_1_s cn63xxp1; 3272 struct cvmx_sli_scratch_1_s cn66xx; 3273 struct cvmx_sli_scratch_1_s cn68xx; 3274 struct cvmx_sli_scratch_1_s cn68xxp1; 3275 struct cvmx_sli_scratch_1_s cnf71xx; 3276}; 3277 3278union cvmx_sli_scratch_2 { 3279 uint64_t u64; 3280 struct cvmx_sli_scratch_2_s { 3281#ifdef __BIG_ENDIAN_BITFIELD 3282 uint64_t data:64; 3283#else 3284 uint64_t data:64; 3285#endif 3286 } s; 3287 struct cvmx_sli_scratch_2_s cn61xx; 3288 struct cvmx_sli_scratch_2_s cn63xx; 3289 struct cvmx_sli_scratch_2_s cn63xxp1; 3290 struct cvmx_sli_scratch_2_s cn66xx; 3291 struct cvmx_sli_scratch_2_s cn68xx; 3292 struct cvmx_sli_scratch_2_s cn68xxp1; 3293 struct cvmx_sli_scratch_2_s cnf71xx; 3294}; 3295 3296union cvmx_sli_state1 { 3297 uint64_t u64; 3298 struct cvmx_sli_state1_s { 3299#ifdef __BIG_ENDIAN_BITFIELD 3300 uint64_t cpl1:12; 3301 uint64_t cpl0:12; 3302 uint64_t arb:1; 3303 uint64_t csr:39; 3304#else 3305 uint64_t csr:39; 3306 uint64_t arb:1; 3307 uint64_t cpl0:12; 3308 uint64_t cpl1:12; 3309#endif 3310 } s; 3311 struct cvmx_sli_state1_s cn61xx; 3312 struct cvmx_sli_state1_s cn63xx; 3313 struct cvmx_sli_state1_s cn63xxp1; 3314 struct cvmx_sli_state1_s cn66xx; 3315 struct cvmx_sli_state1_s cn68xx; 3316 struct cvmx_sli_state1_s cn68xxp1; 3317 struct cvmx_sli_state1_s cnf71xx; 3318}; 3319 3320union cvmx_sli_state2 { 3321 uint64_t u64; 3322 struct cvmx_sli_state2_s { 3323#ifdef __BIG_ENDIAN_BITFIELD 3324 uint64_t reserved_56_63:8; 3325 uint64_t nnp1:8; 3326 uint64_t reserved_47_47:1; 3327 uint64_t rac:1; 3328 uint64_t csm1:15; 3329 uint64_t csm0:15; 3330 uint64_t nnp0:8; 3331 uint64_t nnd:8; 3332#else 3333 uint64_t nnd:8; 3334 uint64_t nnp0:8; 3335 uint64_t csm0:15; 3336 uint64_t csm1:15; 3337 uint64_t rac:1; 3338 uint64_t reserved_47_47:1; 3339 uint64_t nnp1:8; 3340 uint64_t reserved_56_63:8; 3341#endif 3342 } s; 3343 struct cvmx_sli_state2_s cn61xx; 3344 struct cvmx_sli_state2_s cn63xx; 3345 struct cvmx_sli_state2_s cn63xxp1; 3346 struct cvmx_sli_state2_s cn66xx; 3347 struct cvmx_sli_state2_s cn68xx; 3348 struct cvmx_sli_state2_s cn68xxp1; 3349 struct cvmx_sli_state2_s cnf71xx; 3350}; 3351 3352union cvmx_sli_state3 { 3353 uint64_t u64; 3354 struct cvmx_sli_state3_s { 3355#ifdef __BIG_ENDIAN_BITFIELD 3356 uint64_t reserved_56_63:8; 3357 uint64_t psm1:15; 3358 uint64_t psm0:15; 3359 uint64_t nsm1:13; 3360 uint64_t nsm0:13; 3361#else 3362 uint64_t nsm0:13; 3363 uint64_t nsm1:13; 3364 uint64_t psm0:15; 3365 uint64_t psm1:15; 3366 uint64_t reserved_56_63:8; 3367#endif 3368 } s; 3369 struct cvmx_sli_state3_s cn61xx; 3370 struct cvmx_sli_state3_s cn63xx; 3371 struct cvmx_sli_state3_s cn63xxp1; 3372 struct cvmx_sli_state3_s cn66xx; 3373 struct cvmx_sli_state3_s cn68xx; 3374 struct cvmx_sli_state3_s cn68xxp1; 3375 struct cvmx_sli_state3_s cnf71xx; 3376}; 3377 3378union cvmx_sli_tx_pipe { 3379 uint64_t u64; 3380 struct cvmx_sli_tx_pipe_s { 3381#ifdef __BIG_ENDIAN_BITFIELD 3382 uint64_t reserved_24_63:40; 3383 uint64_t nump:8; 3384 uint64_t reserved_7_15:9; 3385 uint64_t base:7; 3386#else 3387 uint64_t base:7; 3388 uint64_t reserved_7_15:9; 3389 uint64_t nump:8; 3390 uint64_t reserved_24_63:40; 3391#endif 3392 } s; 3393 struct cvmx_sli_tx_pipe_s cn68xx; 3394 struct cvmx_sli_tx_pipe_s cn68xxp1; 3395}; 3396 3397union cvmx_sli_win_rd_addr { 3398 uint64_t u64; 3399 struct cvmx_sli_win_rd_addr_s { 3400#ifdef __BIG_ENDIAN_BITFIELD 3401 uint64_t reserved_51_63:13; 3402 uint64_t ld_cmd:2; 3403 uint64_t iobit:1; 3404 uint64_t rd_addr:48; 3405#else 3406 uint64_t rd_addr:48; 3407 uint64_t iobit:1; 3408 uint64_t ld_cmd:2; 3409 uint64_t reserved_51_63:13; 3410#endif 3411 } s; 3412 struct cvmx_sli_win_rd_addr_s cn61xx; 3413 struct cvmx_sli_win_rd_addr_s cn63xx; 3414 struct cvmx_sli_win_rd_addr_s cn63xxp1; 3415 struct cvmx_sli_win_rd_addr_s cn66xx; 3416 struct cvmx_sli_win_rd_addr_s cn68xx; 3417 struct cvmx_sli_win_rd_addr_s cn68xxp1; 3418 struct cvmx_sli_win_rd_addr_s cnf71xx; 3419}; 3420 3421union cvmx_sli_win_rd_data { 3422 uint64_t u64; 3423 struct cvmx_sli_win_rd_data_s { 3424#ifdef __BIG_ENDIAN_BITFIELD 3425 uint64_t rd_data:64; 3426#else 3427 uint64_t rd_data:64; 3428#endif 3429 } s; 3430 struct cvmx_sli_win_rd_data_s cn61xx; 3431 struct cvmx_sli_win_rd_data_s cn63xx; 3432 struct cvmx_sli_win_rd_data_s cn63xxp1; 3433 struct cvmx_sli_win_rd_data_s cn66xx; 3434 struct cvmx_sli_win_rd_data_s cn68xx; 3435 struct cvmx_sli_win_rd_data_s cn68xxp1; 3436 struct cvmx_sli_win_rd_data_s cnf71xx; 3437}; 3438 3439union cvmx_sli_win_wr_addr { 3440 uint64_t u64; 3441 struct cvmx_sli_win_wr_addr_s { 3442#ifdef __BIG_ENDIAN_BITFIELD 3443 uint64_t reserved_49_63:15; 3444 uint64_t iobit:1; 3445 uint64_t wr_addr:45; 3446 uint64_t reserved_0_2:3; 3447#else 3448 uint64_t reserved_0_2:3; 3449 uint64_t wr_addr:45; 3450 uint64_t iobit:1; 3451 uint64_t reserved_49_63:15; 3452#endif 3453 } s; 3454 struct cvmx_sli_win_wr_addr_s cn61xx; 3455 struct cvmx_sli_win_wr_addr_s cn63xx; 3456 struct cvmx_sli_win_wr_addr_s cn63xxp1; 3457 struct cvmx_sli_win_wr_addr_s cn66xx; 3458 struct cvmx_sli_win_wr_addr_s cn68xx; 3459 struct cvmx_sli_win_wr_addr_s cn68xxp1; 3460 struct cvmx_sli_win_wr_addr_s cnf71xx; 3461}; 3462 3463union cvmx_sli_win_wr_data { 3464 uint64_t u64; 3465 struct cvmx_sli_win_wr_data_s { 3466#ifdef __BIG_ENDIAN_BITFIELD 3467 uint64_t wr_data:64; 3468#else 3469 uint64_t wr_data:64; 3470#endif 3471 } s; 3472 struct cvmx_sli_win_wr_data_s cn61xx; 3473 struct cvmx_sli_win_wr_data_s cn63xx; 3474 struct cvmx_sli_win_wr_data_s cn63xxp1; 3475 struct cvmx_sli_win_wr_data_s cn66xx; 3476 struct cvmx_sli_win_wr_data_s cn68xx; 3477 struct cvmx_sli_win_wr_data_s cn68xxp1; 3478 struct cvmx_sli_win_wr_data_s cnf71xx; 3479}; 3480 3481union cvmx_sli_win_wr_mask { 3482 uint64_t u64; 3483 struct cvmx_sli_win_wr_mask_s { 3484#ifdef __BIG_ENDIAN_BITFIELD 3485 uint64_t reserved_8_63:56; 3486 uint64_t wr_mask:8; 3487#else 3488 uint64_t wr_mask:8; 3489 uint64_t reserved_8_63:56; 3490#endif 3491 } s; 3492 struct cvmx_sli_win_wr_mask_s cn61xx; 3493 struct cvmx_sli_win_wr_mask_s cn63xx; 3494 struct cvmx_sli_win_wr_mask_s cn63xxp1; 3495 struct cvmx_sli_win_wr_mask_s cn66xx; 3496 struct cvmx_sli_win_wr_mask_s cn68xx; 3497 struct cvmx_sli_win_wr_mask_s cn68xxp1; 3498 struct cvmx_sli_win_wr_mask_s cnf71xx; 3499}; 3500 3501union cvmx_sli_window_ctl { 3502 uint64_t u64; 3503 struct cvmx_sli_window_ctl_s { 3504#ifdef __BIG_ENDIAN_BITFIELD 3505 uint64_t reserved_32_63:32; 3506 uint64_t time:32; 3507#else 3508 uint64_t time:32; 3509 uint64_t reserved_32_63:32; 3510#endif 3511 } s; 3512 struct cvmx_sli_window_ctl_s cn61xx; 3513 struct cvmx_sli_window_ctl_s cn63xx; 3514 struct cvmx_sli_window_ctl_s cn63xxp1; 3515 struct cvmx_sli_window_ctl_s cn66xx; 3516 struct cvmx_sli_window_ctl_s cn68xx; 3517 struct cvmx_sli_window_ctl_s cn68xxp1; 3518 struct cvmx_sli_window_ctl_s cnf71xx; 3519}; 3520 3521#endif 3522